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| freescale.com microcontrollers m68hc08 mc68HC908JK1 mc68hrc908jk1 mc68HC908JK3 jc68hrc908jk3 mc68hc908jl3 mc68hrc908jl3 technical data rev. 1.1 mc68hc908jl3/h august 1, 2005
mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor list of sections 3 technical data ? mc68h(r)c908jl3 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 21 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 section 3. random-a ccess memory (ram) . . . . . . . . . . 37 section 4. flash memory (flash) . . . . . . . . . . . . . . . . 39 section 5. configuration register (config) . . . . . . . . . 47 section 6. central processor unit (cpu) . . . . . . . . . . . . 51 section 7. system integration mo dule (sim) . . . . . . . . . 71 section 8. oscillator (osc ) . . . . . . . . . . . . . . . . . . . . . . . 95 section 9. monitor rom (mon) . . . . . . . . . . . . . . . . . . . 101 section 10. timer interface module (tim) . . . . . . . . . . . 115 section 11. analog-to-digital converter (adc) . . . . . . 137 section 12. i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 section 13. external interrupt (irq ) . . . . . . . . . . . . . . . 159 section 14. keyboard interrupt module (kbi). . . . . . . . 165 section 15. computer operatin g properly (cop) . . . . 173 section 16. low voltage inhibit (l vi) . . . . . . . . . . . . . . 179 section 17. break module (break) . . . . . . . . . . . . . . . 183 section 18. electrical sp ecifications. . . . . . . . . . . . . . . 191 section 19. mechanical specificati ons . . . . . . . . . . . . . 203 section 20. ordering in formation . . . . . . . . . . . . . . . . . 207 list of sections technical data mc68h(r)c908jl3 ? rev. 1.1 4 list of sections freescale semiconductor mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor table of contents 5 technical data ? mc68h(r)c908jl3 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 section 4. flash memory (flash) 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table of contents technical data mc68h(r)c908jl3 ? rev. 1.1 6 table of contents freescale semiconductor 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 4.9 flash block protect regist er . . . . . . . . . . . . . . . . . . . . . . . . . 46 section 5. configurat ion register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 section 6. central pr ocessor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table of contents mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor table of contents 7 section 7. system integration module (sim) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 75 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.2 clock start-up from por . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 75 7.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 76 7.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 77 7.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.4.2.2 computer operati ng properly (cop) reset. . . . . . . . . . . 79 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.4.2.5 lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . . 80 7.5.2 sim counter during stop mode reco very . . . . . . . . . . . . . . 80 7.5.3 sim counter and reset st ates. . . . . . . . . . . . . . . . . . . . . . . 81 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 86 7.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . . 86 7.6.2.3 interrupt stat us register 3 . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . . 87 7.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table of contents technical data mc68h(r)c908jl3 ? rev. 1.1 8 table of contents freescale semiconductor 7.8.1 break status register (bsr) . . . . . . . . . . . . . . . . . . . . . . . .91 7.8.2 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . 92 7.8.3 break flag control register (bfcr) . . . . . . . . . . . . . . . . . . 94 section 8. oscillator (osc) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.3 x-tal oscillator (mc68 hc908xxx). . . . . . . . . . . . . . . . . . . . . . . 96 8.4 rc oscillator (mc68hrc9 08xxx) . . . . . . . . . . . . . . . . . . . . . . 97 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 98 8.5.2 crystal amplifier output pi n (osc2/pta6/rcclk) . . . . . . . 98 8.5.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 98 8.5.4 x-tal oscillator clo ck (xtalclk). . . . . . . . . . . . . . . . . . . . .98 8.5.5 rc oscillator clock ( rcclk). . . . . . . . . . . . . . . . . . . . . . . . 99 8.5.6 oscillator out 2 (2oscout ) . . . . . . . . . . . . . . . . . . . . . . . .99 8.5.7 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.7 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . 100 section 9. monitor rom (mon) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 9.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.4.2 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 9.4.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.4 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table of contents mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor table of contents 9 9.4.6 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 section 10. timer interface module (tim) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 120 10.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .120 10.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 121 10.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 122 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 123 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 10.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . . 127 10.10.2 tim counter regist ers (tcnth:tcntl) . . . . . . . . . . . . . . 129 10.10.3 tim counter modul o registers (tmodh:tm odl) . . . . . . 130 10.10.4 tim channel status and co ntrol registers (tsc0:tsc1) . 131 10.10.5 tim channel registers (tch0h /l:tch1h/l) . . . . . . . . . . 135 table of contents technical data mc68h(r)c908jl3 ? rev. 1.1 10 table of contents freescale semiconductor section 11. analog-to-dig ital converter (adc) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 11.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 11.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.7.1 adc voltage in ( adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .142 11.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 145 section 12. i/o ports 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.4 port a data register (pta ) . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.4.1 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 150 12.4.2 port a input pull-up enable register (pta pue) . . . . . . . . 151 12.5 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.5.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 153 12.5.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 153 table of contents mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor table of contents 11 12.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 155 12.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 156 12.6.3 port d control register (pdcr). . . . . . . . . . . . . . . . . . . . . 157 section 13. external interrupt (irq) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 13.4.1 irq1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 163 13.6 irq status and control register (iscr) . . . . . . . . . . . . . . . . 163 section 14. keyboard in terrupt module (kbi) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 14.4.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.4.2 keyboard status and control register. . . . . . . . . . . . . . . . 169 14.4.3 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 170 14.5 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.6 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.7 keyboard module during break interrupts . . . . . . . . . . . . . . . 171 section 15. computer op erating properly (cop) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 table of contents technical data mc68h(r)c908jl3 ? rev. 1.1 12 table of contents freescale semiconductor 15.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.1 2oscout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15.4.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15.4.3 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.5 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.4.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.4.7 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 176 15.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 15.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 178 section 16. low voltage inhibit (lvi) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 16.5 lvi control register (config2/con fig1) . . . . . . . . . . . . . . 180 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 section 17. break module (break) 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table of contents mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor table of contents 13 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 17.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 186 17.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .186 17.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 186 17.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 186 17.5 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 17.5.1 break status and control regist er (brkscr) . . . . . . . . . 187 17.5.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 188 17.5.3 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 17.5.4 break flag control register (bfcr) . . . . . . . . . . . . . . . . . 190 17.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 17.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 17.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 section 18. electrical specifications 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 18.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.6 5v dc electrical characte ristics. . . . . . . . . . . . . . . . . . . . . . . 194 18.7 5v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 18.8 5v oscillator charac teristics. . . . . . . . . . . . . . . . . . . . . . . . . . 196 18.9 3v dc electrical characte ristics. . . . . . . . . . . . . . . . . . . . . . . 197 18.10 3v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 18.11 3v oscillator characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 199 18.12 typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 18.13 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18.14 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table of contents technical data mc68h(r)c908jl3 ? rev. 1.1 14 table of contents freescale semiconductor section 19. mechanic al specifications 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.3 20-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.4 20-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.5 28-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19.6 28-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 section 20. ordering information 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 20.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor list of figures 15 technical data ? mc68h(r)c908jl3 list of figures figure title page 1-1 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1-2 mcu pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . .30 4-1 flash control regist er (flcr) . . . . . . . . . . . . . . . . . . . . . . . 40 4-2 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 45 4-3 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 46 5-1 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . . 48 5-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . . 49 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 56 7-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .74 7-3 sim clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 7-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 7-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7-8 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7-9 interrupt entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7-10 interrupt recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 list of figures technical data mc68h(r)c908jl3 ? rev. 1.1 16 list of figures freescale semiconductor figure title page 7-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . . 84 7-12 interrupt status register 1 (int1). . . . . . . . . . . . . . . . . . . . . . . 86 7-13 interrupt status register 2 (int2). . . . . . . . . . . . . . . . . . . . . . . 86 7-14 interrupt status register 3 (int3). . . . . . . . . . . . . . . . . . . . . . . 87 7-15 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7-16 wait recovery from interrupt or br eak . . . . . . . . . . . . . . . . . . . 89 7-17 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . . 89 7-18 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7-19 stop mode recovery from interrupt or break . . . . . . . . . . . . . . 91 7-20 break status register (b sr) . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7-21 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7-22 break flag control register (bfcr) . . . . . . . . . . . . . . . . . . . . 94 8-1 x-tal oscillator external connections . . . . . . . . . . . . . . . . . . . . 96 8-2 rc oscillator external connections . . . . . . . . . . . . . . . . . . . . .97 9-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9-2 low-voltage monitor m ode entry flowchart. . . . . . . . . . . . . . 106 9-3 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9-4 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9-5 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 9-6 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 9-7 monitor mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . .113 10-1 tim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10-2 tim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .118 10-3 pwm period and pulse wi dth . . . . . . . . . . . . . . . . . . . . . . . . 122 10-4 tim status and control register (tsc ) . . . . . . . . . . . . . . . . . 127 10-5 tim counter register s (tcnth:tcntl) . . . . . . . . . . . . . . . . 130 10-6 tim counter modulo registers (tmodh:tmodl) . . . . . . . . . 131 10-7 tim channel status and contro l registers (tsc0:tsc1) . . . 132 10-8 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 10-9 tim channel registers (tch0h/l:t ch1h/l). . . . . . . . . . . . . 136 11-1 adc i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11-2 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11-3 adc status and control register (adscr) . . . . . . . . . . . . . . 142 list of figures mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor list of figures 17 figure title page 11-4 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11-5 adc input clock register (adiclk) . . . . . . . . . . . . . . . . . . . 145 12-1 i/o port register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .148 12-2 port a data register (pta ) . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 150 12-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12-5 port a input pull-up e nable register (ptapue) . . . . . . . . . . 152 12-6 port b data register (ptb ) . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12-7 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 153 12-8 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12-9 port d data register (ptd ) . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12-10 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 156 12-11 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12-12 port d control register (pdcr) . . . . . . . . . . . . . . . . . . . . . . . 157 13-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13-2 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .161 13-3 irq status and contro l register (intscr) . . . . . . . . . . . . . . 163 13-4 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . 164 14-1 kbi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .166 14-2 keyboard interrupt block diagram . . . . . . . . . . . . . . . . . . . . . 166 14-3 keyboard status and control register (kbscr) . . . . . . . . . . 169 14-4 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 170 15-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . 176 15-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 177 16-1 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .180 16-2 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . 180 16-3 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . 181 17-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 185 17-2 break i/o register summ ary . . . . . . . . . . . . . . . . . . . . . . . . . 185 17-3 break status and control register (brkscr). . . . . . . . . . . . 187 list of figures technical data mc68h(r)c908jl3 ? rev. 1.1 18 list of figures freescale semiconductor figure title page 17-4 break address register high (brkh) . . . . . . . . . . . . . . . . . . 188 17-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 188 17-6 break status register (b sr) . . . . . . . . . . . . . . . . . . . . . . . . . 188 17-7 break flag control register (bfcr) . . . . . . . . . . . . . . . . . . . 190 18-1 rc vs. frequency (5v @25 c) . . . . . . . . . . . . . . . . . . . . . . .196 18-2 rc vs. frequency (3v @25 c) . . . . . . . . . . . . . . . . . . . . . . .199 18-3 typical operating idd, wi th all modules turned on (25 c) . 200 18-4 typical wait mode idd, with adc tur ned on (25 c) . . . . . . 200 18-5 typical stop mode idd, wi th all module s disabled (25 c) . . 200 19-1 20-pin pdip (case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19-2 20-pin soic (case #751d) . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19-3 28-pin pdip (case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19-4 28-pin soic (case #751f). . . . . . . . . . . . . . . . . . . . . . . . . . .205 mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor list of tables 19 technical data ? mc68h(r)c908jl3 list of tables table title page 1-1 summary of device variat ions . . . . . . . . . . . . . . . . . . . . . . . . . 21 1-2 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7-1 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7-3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7-4 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9-1 monitor mode entry r equirements and options. . . . . . . . . . . 104 9-2 monitor mode vector diffe rences . . . . . . . . . . . . . . . . . . . . . . 107 9-3 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 107 9-4 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 110 9-5 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 110 9-6 iread (indexed read) co mmand . . . . . . . . . . . . . . . . . . . . . 111 9-7 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . . 111 9-8 readsp (read stack po inter) command . . . . . . . . . . . . . . . 112 9-9 run (run user program) command . . . . . . . . . . . . . . . . . . . 112 10-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 134 11-1 mux channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11-2 adc clock divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 list of tables technical data mc68h(r)c908jl3 ? rev. 1.1 20 list of tables freescale semiconductor table title page 12-1 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 12-2 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12-3 port d pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 18-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18-2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 18-3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 18-4 dc electrical characteristics (5v) . . . . . . . . . . . . . . . . . . . . . 194 18-5 control timing (5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 18-6 oscillator component specif ications (5v) . . . . . . . . . . . . . . . 196 18-7 dc electrical characteristics (3v) . . . . . . . . . . . . . . . . . . . . . 197 18-8 control timing (3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 18-9 oscillator component specif ications (3v) . . . . . . . . . . . . . . . 199 18-10 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18-11 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 20-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor general description 21 technical data ? mc68h(r)c908jl3 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.2 introduction the mc68h(r)c908jl3 is a member of the low-cost, high-performance m68hc08 family of 8-bi t microcontroller units (mcus). the m68hc08 family is based on the customer-spec ified integrated circuit (csic) design strategy. all mcus in t he family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. all references to the mc68h(r)c908jl3 in this data book apply equally to the mc68h(r)c908jk3 and mc 68h(r)c908jk1, unless otherwise stated. table 1-1. summary of device variations device flash memory size pin count mc68h(r)c908jl3 4096 bytes 28 pins mc68h(r)c908jk3 4096 bytes 20 pins mc68h(r)c908jk1 1536 bytes 20 pins general description technical data mc68h(r)c908jl3 ? rev. 1.1 22 general description freescale semiconductor 1.3 features features of the mc68h(r)c908 jl3 include the following: high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families low-power design; fully st atic with stop and wait modes 5v and 3v operating voltages 8mhz internal bus operation rc-oscillator circuit or crystal-oscillator options in-system flash programming flash security 1 user flash memory ? 4096 bytes for mc68h(r)c908jl3/jk3 ? 1536 bytes for mc68h(r)c908jk1 128 bytes of on-chip r andom-access memory (ram) 2-channel, 16-bit timer in terface module (tim) 12-channel, 8-bit analog-to -digital converter (adc) 23 general purpose i/o ports for mc68h(r)c908jl3: ? 7 keyboard interrupt with internal pull-up ? 10 led drivers ?2 25ma open-drain i/o with pull-up ? 2 icap/ocap/pwm 15 general purpose i/o ports for mc68h(r)c908jk3/jk1: ? 1 keyboard interrupt with internal pull-up (with rc oscillat or option selected) ? 4 led drivers ?2 25ma open-drain i/o with pull-up ? 2 icap/ocap/pwm 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. general description mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor general description 23 system protection features: ? optional computer operati ng properly (cop) reset ? optional low-voltage detection with reset and selectable trip points for 3v an d 5v operation. ? illegal opcode detection with reset ? illegal address detection with reset master reset pin with intern al pull-up and power-on reset irq1 with programmable pull- up and schmitt-t rigger input 28-pin pdip and 28-pin soic packages for mc68h(r)c908jl3 20-pin pdip and 20-pi n soic packages for mc68h(r)c908jk3/jk1 features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support 1.4 mcu block diagram figure 1-1 shows the structure of the mc68h(r)c908jl3. general description technical data mc68h(r)c908jl3 ? rev. 1.1 24 general description freescale semiconductor figure 1-1. mcu block diagram rst , irq1 : pin has internal 30k pull-up ptd[6:7]: pins have 25ma open-drain output & programmable 5k pull-up pta[0:5], ptd[2:3], ptd[6:7]: pin has led drive pta[0:6]: pins have programmable keyboard interrupt and pull-up pta[0:5] and ptd[0:1]: not available on 20-pin devices ? mc68h(r)c908jk3/jk1 mc68h(r)c908jl3/jk3: 4096 bytes mc68h(r)c908jk1: 1536 bytes user flash cond code reg v 1 1 i n z c h index reg cpu control stk pntr alu 68hc08 cpu accum program counter cpu registers 128 bytes ram osc1 rst irq1 vdd vss 16-bit timer module cop module power-on reset module break module mode select module system integration module x-tal oscillator or rc-oscillator power supply and voltage regulator ptb[0:7] ptb ddrb monitor rom 960 bytes ptd[0:7] pta/kbi[0:6] 8-bit adc adc[0:7]/ ptb[0:7] tch0/ptd4 tch1/ptd5 osc2/rcclk/pta6 ptd ddrd pta ddra adc[11:8]/ ptd[0:3] general description mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor general description 25 1.5 pin assignments the mc68h(r)c908jl3 is availabl e in 28-pin packages and the mc68h(r)c908jk3/jk1 in 20-pin packages. figure 1-2 shows the pin assignment for the two packages. figure 1-2. mcu pin assignments 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 18 12 13 14 17 16 15 8 9 10 11 1 2 3 4 5 6 7 20 19 18 17 16 15 14 13 12 11 8 9 10 rst pta5 ptd4 ptd5 ptd2 pta4 ptd3 ptb0 ptb1 ptd1 ptb2 ptb3 ptd0 ptb4 irq1 pta0 vss osc1 osc2/pta6 pta1 vdd pta2 pta3 ptb7 ptb6 ptb5 ptd7 ptd6 rst ptd4 ptd5 ptd2 ptd3 ptb0 ptb1 ptb2 ptb3 ptb4 irq1 vss osc1 osc2/pta6 vdd ptb7 ptb6 ptb5 ptd7 ptd6 28-pin assignment mc68h(r)c908jl3 20-pin assignment mc68h(r)c908jk3/jk1 pins not bonded out on 20-pin package: pta0, pta1, pta2, pta3, pta4, pta5, ptd0, ptd1. general description technical data mc68h(r)c908jl3 ? rev. 1.1 26 general description freescale semiconductor 1.6 pin functions description of the pin f unctions are provided in table 1-2 . note: on the 20-pin package, the following pins are not available: pta0, pta1, pta2, pta3, pt a4, pta5, ptd0, and ptd1. table 1-2. pin functions pin name pin description in/out voltage level vdd power supply. in 5v or 3v vss power supply ground out 0v rst reset input, active low. with internal pull-up and schmitt trigger input. input vdd irq1 external irq pin. with software programmable internal pull-up and schmitt trigger input. this pin is also used for mode entry selection. input vdd to vdd+v hi osc1 x-tal or rc oscillator input. in analog osc2 for x-tal oscillator option: x-tal oscillator output, this is the inverting osc1 signal. out analog for rc oscillator option: default is rcclk output. shared with pta6/kbi6, with programmable pull-up. in/out vdd pta[0:6] 7-bit general purpose i/o port. in/out vdd shared with 7 keyboard interrupts kbi[0:6]. in vdd each pin has programmable internal pull-up device. in vdd ptb[0:7] 8-bit general purpose i/o port. in/out vdd shared with 8 adc inputs, adc[0:7]. in analog ptd[0:7] 8-bit general purpose i/o port. in/out vdd ptd[3:0] shared with 4 adc inputs, adc[8:11]. input analog ptd[4:5] shared with tim channels, tch0 and tch1. in/out vdd ptd[6:7] can be configured as 25ma open-drain output with pull-up. in/out vdd mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor memory 27 technical data ? mc68h(r)c908jl3 section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.2 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 4096 bytes of user fla sh for mc68h(r)c908jl3/jk3 1536 bytes of user flash for mc68h(r)c908jk1 128 bytes of ram 48 bytes of user-defined vectors 960 bytes of monitor rom memory technical data mc68h(r)c908jl3 ? rev. 1.1 28 memory freescale semiconductor $0000 $003f i/o registers 64 bytes $0040 $007f reserved 64 bytes $0080 $00ff ram 128 bytes $0100 $ebff unimplemented 60160 bytes unimplemented 62720 bytes $0100 $f5ff $ec00 $fbff flash memory mc68h(r)c908jl3/jk3 4096 bytes flash memory mc68h(r)c908jk1 1536 bytes $f600 $fbff $fc00 $fdff monitor rom 512 bytes $fe00 break status register (bsr) $fe01 reset status register (rsr) $fe02 reserved (ubar) $fe03 break flag control register (bfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 interrupt status register 3 (int3) $fe07 reserved $fe08 flash control register (flcr) $fe09 flash block protect register (flbpr) $fe0a reserved $fe0b reserved $fe0c break address high register (brkh) $fe0d break address low register (brkl) $fe0e break status and control register (brkscr) $fe0f reserved $fe10 $ffcf monitor rom 448 bytes $ffd0 $ffff user vectors 48 bytes figure 2-1. memory map memory mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor memory 29 2.3 i/o section addresses $0000?$003f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have the following addresses: $fe00 (break status register, bsr) $fe01 (reset status register, rsr) $fe02 (reserved, subar) $fe03 (break flag co ntrol register, bfcr) $fe04 (interrupt status register 1, int1) $fe05 (interrupt status register 2, int2) $fe06 (interrupt status register 3, int3) $fe07 (reserved) $fe08 (flash contro l register, flcr) $fe09 (flash block prot ect register, flbpr) $fe0a (reserved) $fe0b (reserved) $fe0c (break addre ss register high, brkh) $fe0d (break address register low, brkl) $fe0e (break status and control register, brkscr) $fe0f (reserved) $ffff (cop contro l register, copctl) 2.4 monitor rom the 960 bytes at addresses $fc00?$fdff and $fe10?$ffcf are reserved rom addresses that contain the instructions for the monitor functions. (see section 9. monitor rom (mon) .) memory technical data mc68h(r)c908jl3 ? rev. 1.1 30 memory freescale semiconductor addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: 0 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 unimplemented read: write: $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: 0 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 unimplemented read: write: $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 $0009 unimplemented read: write: $000a port d control register (pdcr) read: 0000 slowd7 slowd6 ptdpu7 ptdpu6 write: reset:00000000 = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 1 of 5) memory mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor memory 31 $000b $000c unimplemented read: write: $000d port a input pull-up enable register (ptapue) read: pta6en ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000e $0019 unimplemented read: write: $001a keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) read: 0 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001c unimplemented read: write: $001d irq status and control register (intscr) read: 0000irqf10 imask1 mode1 write: ack1 reset:00000000 $001e configuration register 2 (config2) ? read: irqpud r r lvit1 lvit0 r r r write: reset:0000*0*000 $001f configuration register 1 (config1) ? read: coprs r r lvid r ssrec stop copd write: reset:00000000 ? one-time writable register after each reset. * lvit1 and lvit0 reset to logic 0 by a power-on reset (por) only. $0020 tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 2 of 5) memory technical data mc68h(r)c908jl3 ? rev. 1.1 32 memory freescale semiconductor $0021 tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $0022 tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $0023 tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $0024 tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0025 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0027 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0028 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $002a tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 3 of 5) memory mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor memory 33 $002b $003b unimplemented read: write: $003c adc status and control register (adscr) read: coco aien adco ch4 ch3 ch2 ch1 ch0 write: reset:00011111 $003d adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset $003e adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 $003f unimplemented read: write: $fe00 break status register (bsr) read: rrrrrr sbsw r write: see note reset: 0 note: writing a l ogic 0 clears sbsw. $fe01 reset status register (rsr) read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: 0 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 4 of 5) memory technical data mc68h(r)c908jl3 ? rev. 1.1 34 memory freescale semiconductor $fe05 interrupt status register 2 (int2) read: if14 0000000 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read: 0000000if15 write:rrrrrrrr reset:00000000 $fe07 reserved read: rrrrrrrr write: $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 $fe0a $fe0b reserved read: rrrrrrrr write: $fe0c break address high register (brkh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0d break address low register (brkl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $ffff cop control register (copctl) read: low byte of reset vector write: writing clears co p counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 5 of 5) memory mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor memory 35 . table 2-1. vector addresses vector priority vector address vector lowest if15 $ffde adc conversion co mplete vector (high) $ffdf adc conversion complete vector (low) if14 $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) if13 to if6 ?not used if5 $fff2 tim overflow vector (high) $fff3 tim overflow vector (low) if4 $fff4 tim channel 1 vector (high) $fff5 tim channel 1 vector (low) if3 $fff6 tim channel 0 vector (high) $fff7 tim channel 0 vector (low) if2 ? not used if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low) memory technical data mc68h(r)c908jl3 ? rev. 1.1 36 memory freescale semiconductor mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor random-access memory (ram) 37 technical data ? mc68h(r)c908jl3 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.2 introduction this section describes the 128 bytes of ram. 3.3 functional description addresses $0080 through $0 0ff are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 128 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff, dire ct addressing mode instructions can access efficiently all page zero ram locations. pa ge zero ram, therefore, provides ideal locati ons for frequently accessed global variables. before processing an interrupt, the cp u uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked. random-access memory (ram) technical data mc68h(r)c908jl3 ? rev. 1.1 38 random-access memory (ram) freescale semiconductor during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation. mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor flash memory (flash) 39 technical data ? mc68h(r)c908jl3 section 4. flash memory (flash) 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 4.9 flash block protect regist er . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.2 introduction this section describes the operat ion of the embedd ed flash memory. the flash memory can be read, pr ogrammed, and erased from a single external supply . the program and erase operations are enabled through the use of an internal charge pump. mc68h(r)c908jl3/jk3: 4096 bytes us er flash from $ec00 ? $fbff. mc68h(r)c908jk1: 1536 bytes user flash from $f600 ? $fbff. flash memory (flash) technical data mc68h(r)c908jl3 ? rev. 1.1 40 flash memory (flash) fre escale semiconductor 4.3 functional description the flash memory consists of an ar ray of 4096 or 15 36 bytes with an additional 48 bytes for us er vectors. the mini mum size of flash memory that can be erased is 64 by tes; and the maximum size of flash memory that can be programmed in a program cycle is 32 bytes (a row). program and erase operatio ns are facilitated through control bits in the flash control register (flcr). detail s for these operat ions appear later in this section. the addr ess ranges for the user memory and vectors are: $ec00 ? $fbff; user memory, 4096 bytes: mc68h(r)c908jl3/jk3 $f600 ? $fbff; user memory, 1536 byte s: mc68h(r)c908jk1 $ffd0 ? $ffff; user interr upt vectors, 48 bytes. note: an erased bit reads as logic 1 and a programmed bit reads as logic 0. a security feature prevents vi ewing of the flash contents. 1 4.4 flash control register the flash control register cont rols flash program and erase operations. hven ? high voltage enable bit this read/write bit enables high vo ltage from the charge pump to the memory for either progra m or erase operation. it can only be set if either pgm=1 or erase =1 and the proper se quence for program or erase is followed. 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. address: $fe08 bit 7654321bit 0 read: 0000 hven mass erase pgm write: reset:00000000 figure 4-1. flash cont rol register (flcr) flash memory (flash) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor flash memory (flash) 41 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit confi gures the memory for mass erase operation or block erase operation when the erase bit is set. 1 = mass erase operation selected 0 = block erase operation selected erase ? erase control bit this read/write bit confi gures the memory for erase operation. this bit and the pgm bit should not be se t to 1 at t he same time. 1 = erase operation selected 0 = erase operation not selected pgm ? program control bit this read/write bit confi gures the memory for program operation. this bit and the erase bit s hould not be set to 1 at the same time. 1 = program operation selected 0 = program operation not selected 4.5 flash block erase operation use the following procedure to erase a block of flash memory. a block consists of 64 consecutive bytes starting from a ddresses $xx00, $xx40, $xx80 or $xxc0. the 48-byte user interr upt vectors area also forms a block. any block within the 4k bytes user memory area ($ec00?$fbff) can be eras ed alone. the 48-byte user interrupt vector blocks can not be erased al one due to security c oncern. mass erase is required to erase this block. 1. set the erase bit and clear the mass bit in th e flash control register. 2. write any data to any flash lo cation within the address range of the block to be erased. 3. wait for a time, t nvs (10 s). 4. set the hven bit. flash memory (flash) technical data mc68h(r)c908jl3 ? rev. 1.1 42 flash memory (flash) fre escale semiconductor 5. wait for a time t erase (1ms). 6. clear the erase bit. 7. wait for a time, t nvh (5 s). 8. clear the hven bit. 9. after time, t rcv (1 s) , the memory can be accessed in read mode again. note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but ot her unrelated operations may occur between the steps. 4.6 flash mass erase operation use the following proc edure to erase the en tire flash memory: 1. set both the erase bit and the mass bit in the flash control register. 2. write any data to any flash lo cation within the flash memory address range. 3. wait for a time, t nvs (10 s). 4. set the hven bit. 5. wait for a time t erase (4ms). 6. clear the erase bit. 7. wait for a time, t nvh1 (100 s). 8. clear the hven bit. 9. after time, t rcv (1 s) , the memory can be accessed in read mode again. note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but ot her unrelated operations may occur between the steps. flash memory (flash) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor flash memory (flash) 43 4.7 flash program operation programming of the flash memory is done on a row basis. a row consists of 32 consecutive bytes starting from a ddresses $xx00, $xx20, $xx40, $xx60, $xx80, $xxa0, $xxc0 or $xxe0. use this step-by-step procedure to pr ogram a row of flash memory: ( figure 4-2 shows a flowchart of th e programming algorithm.) note: in order to avoid program disturbs , the row must be erased before any byte on that ro w is programmed. 1. set the pgm bit. this configur es the memory for program operation and enables the latchi ng of address and data for programming. 2. write any data to any flash lo cation within the address range of the row to be programmed. 3. wait for a time, t nvs (10 s). 4. set the hven bit. 5. wait for a time, t pgs (5 s). 6. write data to the by te being programmed. 7. wait for time, t prog (30 s). 8. repeat step 6 and 7 until all the bytes within the row are programmed. 9. clear the pgm bit. 10. wait for time, t nvh (5 s). 11. clear the hven bit. 12. after time, t rcv (1 s), the memory can be accessed in read mode again. this program sequence is repeated th roughout the memory until all data is programmed. flash memory (flash) technical data mc68h(r)c908jl3 ? rev. 1.1 44 flash memory (flash) fre escale semiconductor note: the time between each flash address change (step 6 to step 6), or the time between the last flash addressed programmed to clearing the pgm bit (step 6 to step 10), must not exceed the maxi mum programming time, t prog max. note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. 4.8 flash protection due to the ability of the on-board charge pump to erase and program the flash memory in the tar get application, provis ion is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash block protect register (flbpr). the flb pr determines the range of the flash memory which is to be prot ected. the range of the protected area starts from a location defined by flbpr and ends to the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or prog ram operations. flash memory (flash) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor flash memory (flash) 45 figure 4-2. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 6 to step 6), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 6 to step 9) note: 1 2 3 4 5 6 7 9 10 11 12 algorithm for programming a row (32 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. flash memory (flash) technical data mc68h(r)c908jl3 ? rev. 1.1 46 flash memory (flash) fre escale semiconductor 4.9 flash block protect register the flash block protect register is implemented as an 8-bit i/o register. the value in th is register determines t he starting address of the protected range within the flash memory. bpr[7:1], bit-0 ? flash protec tion register bits [7:1] these eight bits in flbpr (bit-0 is always 0) represent bits [12:5] of a 16-bit memory address. bits [15:13] are logic 1s and bits [4:0] are logic 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block pr otection. the flash is protected from this start address to the end of flash me mory, at $ffff. with this mechanism, the protect star t address can be xx00, xx40, xx80, or xxc0 within the flash memory. examples of protect start address: address: $fe09 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 figure 4-3. flash block pr otect register (flbpr) bpr[7:0] start of address of protect range $00?$60 the entire flash memory is protected. $62 ( 0110 0010 ) $ec40 (111 0 1100 010 0 0000) $64 ( 0110 0100 ) $ec80 (111 0 1100 100 0 0000) $68 ( 0110 1000 ) $ed00 (111 0 1101 000 0 0000) and so on... $de ( 1101 1110 )$fbc0 (111 1 1011 11 0 0 0000) $fe ( 1111 1110 ) $ffc0 (111 1 1111 110 0 0000) $ff the entire flash memory is not protected. flash memory (flash) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor flash memory (flash) 47 flash memory (flash) technical data mc68h(r)c908jl3 ? rev. 1.1 48 flash memory (flash) fre escale semiconductor mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor configuration register (config) 47 technical data ? mc68h(r)c908jl3 section 5. configuration register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.2 introduction this section describes the config uration registers (config1 and config2). the configurati on registers enables or disables the following options: stop mode recovery time (32 2oscout cycles or 4096 2oscout cycles) stop instruction computer operating pr operly module (cop) cop reset period (coprs), (2 13 ?2 4 ) 2oscout or (2 18 ?2 4 ) 2oscout enable lvi circuit select lvi trip voltage configuration register (config) technical data mc68h(r)c908jl3 ? rev. 1.1 48 configuration register (config) freescale semiconductor 5.3 functional description the configuration register is used in the initialization of various options. the configuration register can be wri tten once after each reset. all of the configuration register bits are clea red during reset. since the various options affect the operat ion of the mcu it is recommended that this register be written immedi ately after reset. the conf iguration register is located at $001e and $001f, and may be read at anytim e. note: the config registers are one-time writable by the user after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 5-1 and figure 5-2 . irqpud ? irq1 pin pull-up control bit 1 = internal pull- up is disconnected 0 = internal pull-up is connected between irq1 pin and v dd lvit1, lvit0 ? low vo ltage inhibit trip vo ltage selection bits detail description of the lvi control signals is given in section 16. address: $001e bit 7654321bit 0 read: irqpud r r lvit1 lvit0 r r r write: reset:000 not affected not affected 000 por:00000000 r=reserved figure 5-1. configuratio n register 2 (config2) configuration register (config) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor configuration register (config) 49 coprs ?tcop reset period selection bit 1 = cop reset cycle = (2 13 ? 2 4 ) 2oscout 0 = cop reset cycle = (2 18 ? 2 4 ) 2oscout lvid ?tlow voltage inhibit disable bit 1 = low voltage i nhibit disabled 0 = low voltage inhibit enabled ssrec ? short stop recovery bit ssrec enables the cpu to ex it stop mode with a delay of 32 oscxclk cycles instead of a 4096 2oscout cycle delay. 1 = stop mode re covery after 32 2oscout cycles 0 = stop mode re covery after 4096 2oscout cycles note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal , do not set t he ssrec bit. stop enables the stop instruction. 1 = stop inst ruction enabled 0 = stop instruction tr eated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 15. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: coprs r r lvid r ssrec stop copd write: reset:00000000 r=reserved figure 5-2. configuratio n register 1 (config1) configuration register (config) technical data mc68h(r)c908jl3 ? rev. 1.1 50 configuration register (config) freescale semiconductor mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 51 technical data ? mc68h(r)c908jl3 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2 introduction the m68hc08 cpu (central proce ssor unit) is an enhanced and fully object-code-compatible vers ion of the m 68hc05 cpu. the cpu08 reference manual (freescale document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. central processor unit (cpu) technical data mc68h(r)c908jl3 ? rev. 1.1 52 central processor unit (cpu ) freescale semiconductor 6.3 features object code fully upward-com patible with m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-regi ster manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decim al (bcd) data handling modular architecture with exp andable internal bu s definition for extension of addressi ng range beyond 64 kbytes low-power stop and wait modes 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu regist ers are not part of the memory map. central processor unit (cpu) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 53 figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) central processor unit (cpu) technical data mc68h(r)c908jl3 ? rev. 1.1 54 central processor unit (cpu ) freescale semiconductor 6.4.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. 6.4.3 stack pointer the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp ) instruction sets the least significant byte to $ff and does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) central processor unit (cpu) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 55 note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, t he stack pointer must point only to ram locations. 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. 6.4.5 condition code register the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. prog ram counter (pc) central processor unit (cpu) technical data mc68h(r)c908jl3 ? rev. 1.1 56 central processor unit (cpu ) freescale semiconductor 5 are set permanently to logic 1. the following paragraphs describe the functions of the cond ition code register. v ? overflow flag the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructi ons bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add-without-car ry (add) or add- with-carry (adc) operat ion. the half-carry flag is required for binary- coded decimal (bcd) arithmetic oper ations. the daa instruction uses the states of the h and c flags to determine t he appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) central processor unit (cpu) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 57 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not sta cked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instru ction pulls the cp u registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipul ation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result central processor unit (cpu) technical data mc68h(r)c908jl3 ? rev. 1.1 58 central processor unit (cpu ) freescale semiconductor c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/l ogic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual (freescale document order number cpu08rm/ad) for a descripti on of the instructions and addressing modes and more detail about the architectu re of the cpu. 6.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.6.1 wait mode the wait instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock central processor unit (cpu) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 59 6.6.2 stop mode the stop instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. afte r exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, t he cpu clock begins running after the oscillator stabilization delay. 6.7 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction regist er with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and retu rns the mcu to normal operation if the break interrupt has been deasserted. 6.8 instruction set summary 6.9 opcode map see table 6-2 . central processor unit (cpu) technical data mc68h(r)c908jl3 ? rev. 1.1 60 central processor unit (cpu ) freescale semiconductor table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ? ?? ??? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ? ? ? ? ? ? rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c central processor unit (cpu) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 61 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ? ? ? ? ? ? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ? ? ? ? ? ? rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) technical data mc68h(r)c908jl3 ? rev. 1.1 62 central processor unit (cpu ) freescale semiconductor brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 63 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? ?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ? ?? ??? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? ??? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? ?? inh 52 7 table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) technical data mc68h(r)c908jl3 ? rev. 1.1 64 central processor unit (cpu ) freescale semiconductor eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 central processor unit (cpu) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 65 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ? ??0 ?? dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ? ?? ??? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ? ? ? ? ? ? inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ? ? ? ? ? ? inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ? ?? ??? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c 0 c b0 b7 central processor unit (cpu) technical data mc68h(r)c908jl3 ? rev. 1.1 66 central processor unit (cpu ) freescale semiconductor ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ? ?? ??? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ?????? inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ?? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ? ? 0 ? ? ? inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c central processor unit (cpu) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 67 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) ?????? inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ? ? ? ? ? ? inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ?? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) technical data mc68h(r)c908jl3 ? rev. 1.1 68 central processor unit (cpu ) freescale semiconductor a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressi ng mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack point er 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increm ent to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location ? set or cleared n negative bit ? not affected table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 69 central processor unit (cpu) table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb central processor unit (cpu) technical data mc68h(r)c908jl3 ? rev. 1.1 70 central processor unit (cpu ) freescale semiconductor mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 71 technical data ? mc68h(r)c908jl3 section 7. system integration module (sim) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 75 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.2 clock start-up from por . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 75 7.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 76 7.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 77 7.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.4.2.2 computer operati ng properly (cop) reset. . . . . . . . . . . 79 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.4.2.5 lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . . 80 7.5.2 sim counter during stop mode reco very . . . . . . . . . . . . . . 80 7.5.3 sim counter and reset st ates. . . . . . . . . . . . . . . . . . . . . . . 81 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 86 7.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . . 86 7.6.2.3 interrupt stat us register 3 . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . . 87 system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 72 system integration module (sim) freescale semiconductor 7.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.8.1 break status register (bsr) . . . . . . . . . . . . . . . . . . . . . . . .91 7.8.2 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . 92 7.8.3 break flag control register (bfcr) . . . . . . . . . . . . . . . . . . 94 7.2 introduction this section describes the system integration module (sim), which supports up to 24 external and/or inte rnal interrupts. together with the cpu, the sim controls all mcu activi ties. a block diagram of the sim is shown in figure 7-1 . figure 7-2 is a summary of the sim i/o registers. the sim is a system state controller t hat coordinates cpu and exception timing. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals ? stop/wait/reset/bre ak entry and recovery ? internal clock control master reset control, includi ng power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture exp andable to 128 interrupt sources system integration module (sim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 73 figure 7-1. sim block diagram table 7-1. signal name conventions signal name description 2oscout buffered clock from the x-tal osc illator circuit or the rc oscillator circuit. oscout the 2oscout frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks. (bus clock = 2oscout 4) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) oscout (from oscillator) internal clocks master reset control reset pin logic illegal opcode (from cpu) illegal address (from address map decoders) cop timeout (from cop module) interrupt sources cpu interface reset control sim counter cop clock 2oscout (from oscillator) 2 usb reset (from usb module) vdd internal pull-up system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 74 system integration module (sim) freescale semiconductor addr.register name bit 7654321bit 0 $fe00 break status register (bsr) read: rrrrrr sbsw r write: note reset:00000000 note: writing a l ogic 0 clears sbsw. $fe01 reset status register (rsr) read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: reset: $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: 0 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 0000000 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read: 0000000if15 write:rrrrrrrr reset:00000000 = unimplemented r = reserved figure 7-2. sim i/o register summary system integration module (sim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 75 7.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, oscout, as shown in figure 7-3 . figure 7-3. sim clock signals 7.3.1 bus timing in user mode , the internal bus frequency is the o scillator frequency (2oscout) divided by four. 7.3.2 clock start-up from por when the power-on reset module generat es a reset, t he clocks to the cpu and peripherals are inactive an d held in an inactive phase until after the 4096 2oscout cycle por time-out has completed. the rst pin is driven low by the sim du ring this entire period. the ibus clocks start upon completion of the time-out. 7.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interr upt, break, or rese t, the sim allows 2oscout to clock the sim counter . the cpu and perip heral clocks do not become active until after the st op delay time-out. this time-out is selectable as 4096 or 32 2oscout cycles. (see 7.7.2 stop mode .) 2 bus clock generators sim sim counter from oscillator from oscillator oscout 2oscout system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 76 system integration module (sim) freescale semiconductor in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 7.4 reset and system initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly module (cop) low-voltage inhi bit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. an internal reset clear s the sim counter (see 7.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the reset status regi ster (rsr). (see 7.8 sim registers .) 7.4.1 external pin reset the rst pin circuits include an internal pull-up device. pulling the asynchronous rst pin low halts all processing. the pin bit of the reset status register (rsr) is set as long as rst is held low for a minimum of 67 2oscclk cycles, assumi ng that the por was not the source of the reset. see table 7-2 for details. figure 7-4 shows the relative timing. table 7-2. pin bit set timing reset type number of cycles required to set pin por 4163 (4096 + 64 + 3) all others 67 (64 + 3) system integration module (sim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 77 figure 7-4. extern al reset timing 7.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 2oscout cycles to allow resetting of external peripherals. the inte rnal reset signal irst continues to be assert ed for an additional 32 cycles ( figure 7-5 ). an internal reset can be caused by an illegal address, illegal opcode, cop time-out, or por. (see figure 7-6 . sources of internal reset .) note that for por resets, the sim cycles through 4096 2oscout cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 7-5 . figure 7-5. inter nal reset timing the cop reset is asynchro nous to the bus clock. figure 7-6. sources of internal reset rst iab pc vect h vect l oscout irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high 2oscout illegal address rst illegal opcode rst coprst por lvi internal reset system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 78 system integration module (sim) freescale semiconductor the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. 7.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pul se to indicate that pow er-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 2oscout cycles. sixty-four 2osc out cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the foll owing events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscill ator to drive 2oscout. internal clocks to the cpu and m odules are held i nactive for 4096 2oscout cycles to allow stab ilization of t he oscillator. the rst pin is driven low during th e oscillator stabilization time. the por bit of the reset status re gister (rsr) is set and all other bits in the register are cleared. figure 7-7. por recovery porrst osc1 2oscout oscout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff system integration module (sim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 79 7.4.2.2 computer operat ing properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the reset status register (rsr). th e sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module time-out, wr ite any value to location $ffff. writing to location $ffff clears the cop counter and stages 12 through 5 of the sim counter. the sim counter output, which occurs at least every (2 12 ? 2 4 ) 2oscout cycles, drives the cop counter. the cop should be serviced as s oon as possible out of reset to guarantee the maximum amount of time before the first time-out. the cop module is disabled if the rst pin or the irq 1 pin is held at v dd +v hi while the mcu is in monito r mode. the cop module can be disabled only through co mbinational logic c onditioned with the high voltage signal on the rst or the irq1 pin. this prevent s the cop from becoming disabled as a result of ex ternal noise. duri ng a break state, v dd +v hi on the rst pin disables the cop module. 7.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets t he ilop bit in the reset st atus register (rsr) and causes a reset. if the stop enable bit, st op, in the mask option regi ster is logic zero, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 7.4.2.4 illegal address reset an opcode fetch from an unm apped address genera tes an illegal address reset. the sim ve rifies that t he cpu is fetching an opcode prior to asserting the ilad bit in the reset stat us register (rsr) and resetting the mcu. a data fetch from an unmapped addre ss does not generate a reset. the sim active ly pulls down the rst pin for all internal reset sources. system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 80 system integration module (sim) freescale semiconductor 7.4.2.5 lvi reset the low-voltage inhibit m odule (lvi) asserts its output to the sim when the v dd voltage falls to th e lvi trip voltage v trip . the lvi bit in the sim reset status register (srsr) is set, and the external re set pin (rstb) is held low while the sim counter coun ts out 4096 2oscclk cycles. sixty- four 2oscout cycles later, the cp u and memories are released from reset to allow the reset vector sequenc e to occur. the sim actively pulls down the (rstb) pin for a ll internal reset sources. 7.5 sim counter the sim counter is used by the pow er-on reset module (por) and in stop mode recovery to allow the os cillator time to stabilize before enabling the internal bus (i bus) clocks. the sim c ounter also serves as a prescaler for the computer operati ng properly module (cop). the sim counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of sim counters and supplies the cl ock for the cop module. the sim counter is clo cked by the falli ng edge of 2oscout. 7.5.1 sim counter during power-on reset the power-on reset module (por) dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to drive the bus clock state machine. 7.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. af ter an interrupt, brea k, or reset, the sim senses the state of the short st op recovery bit, ssrec, in the mask option register. if the s srec bit is a logic one, t hen the stop recovery is reduced from the normal delay of 4096 2oscout cycles down to 32 2oscout cycles. this is ideal for appl ications using canned oscillators that do not require long start-up times from st op mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared in the configurat ion register (config). system integration module (sim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 81 7.5.3 sim counter and reset states external reset has no effect on the sim counter. (see 7.7.2 stop mode for details.) the sim counter is free -running after all re set states. (see 7.4.2 active resets from internal sources for counter control and internal reset re covery sequences.) 7.6 exception control normal, sequential progra m execution can be chang ed in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 7.6.1 interrupts an interrupt temporarily changes th e sequence of program execution to respond to a parti cular event. figure 7-8 flow charts the handling of system interrupts. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serv iced (or the i bit is cleared). system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 82 system integration module (sim) freescale semiconductor figure 7-8. interrupt processing no no no yes no no yes no yes yes (as many interrupts as exist on chip) i bit set? from reset break interrupt? i bit set? irq interrupt? timer interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes system integration module (sim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 83 at the beginning of an interrupt, the cpu sa ves the cpu register contents on the sta ck and sets the interrupt ma sk (i bit) to prevent additional interrupts. at the end of an interrupt , the rti instruction recovers the cpu regist er contents from the stack so that normal processing can resume. figure 7-9 shows interrupt entry timing. figure 7-10 shows interrupt recovery timing. figure 7-9 . interrupt entry figure 7-10. in terrupt recovery 7.6.1.1 hardware interrupts a hardware interrupt does not stop the current in struction. processing of a hardware interrupt begins after completion of t he current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts ar e not masked (i bit clear in the condition code register), and if the corres ponding interrupt enable bit is module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i bit system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 84 system integration module (sim) freescale semiconductor set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 7-11 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda in struction is executed. figure 7-11 . interrupt recognition example the lda opcode is pr efetched by both th e int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine system integration module (sim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 85 7.6.1.2 swi instruction the swi instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 7.6.2 interrupt status registers the flags in the interrupt status re gisters identify maskable interrupt sources. table 7-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. table 7-3. interrupt sources priority source flag mask 1 int register flag vector address highest reset ? ? ? $fffe?$ffff swi instruction ? ? ? $fffc?$fffd irq 1 pin irqf1 imask1 if1 $fffa?$fffb timer channel 0 interrupt ch0f ch0ie if3 $fff6?$fff7 timer channel 1 interrupt ch1f ch1ie if4 $fff4?$fff5 timer overflow interrupt tof toie if5 $fff2?$fff3 keyboard interrupt keyf imaskk if14 $ffe0?$ffe1 lowest adc conversion complete interrupt coco aien if15 $ffde?$ffdf note: 1. the i bit in the condition code register is a global mask for all interrupts sources except the swi instruction. system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 86 system integration module (sim) freescale semiconductor 7.6.2.1 interrupt status register 1 i f 1, i f 3 to if5 ? interrupt flags these flags indicate the presence of interrupt r equests from the sources shown in table 7-3 . 1 = interrupt request present 0 = no interrupt request present bit 0, 1, 3 and 7 ? always read 0 7.6.2.2 interrupt status register 2 i f 14 ? interrupt flags this flag indicates the presence of interrupt r equests from the sources shown in table 7-3 . 1 = interrupt request present 0 = no interrupt request present bit 0 to 6 ? always read 0 address: $fe04 bit 7654321bit 0 read: 0 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 7-12. interrupt st atus register 1 (int1) address: $fe05 bit 7654321bit 0 read: if14 0000000 write:rrrrrrrr reset:00000000 r= reserved figure 7-13. interrupt st atus register 2 (int2) system integration module (sim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 87 7.6.2.3 interrupt status register 3 i f 15 ? interrupt flags these flags indicate the presence of interrupt r equests from the sources shown in table 7-3 . 1 = interrupt request present 0 = no interrupt request present bit 1 to 7 ? always read 0 7.6.3 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. 7.6.4 break interrupts the break module can st op normal program flow at a software- programmable break point by asserti ng its break interrupt output. (see section 17. break module (break) .) the sim puts t he cpu into the break state by forcing it to the swi vector loca tion. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 7.6.5 status flag protection in break mode the sim controls whether status fl ags contained in ot her modules can be cleared during break m ode. the user can sele ct whether flags are address: $fe06 bit 7654321bit 0 read: 0000000if15 write:rrrrrrrr reset:00000000 r= reserved figure 7-14. interrupt st atus register 3 (int3) system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 88 system integration module (sim) freescale semiconductor protected from being clea red by properly initiali zing the break clear flag enable bit (bcfe) in the break flag contro l register (bfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mo de without losing stat us flag information. setting the bcfe bit e nables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step cleari ng mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 7.7 low-power modes executing the wait or stop instruction puts t he mcu in a low-power- consumption mode for st andby situations. the s im holds the cpu in a non-clocked state. the operation of eac h of these mode s is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 7.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 7-15 shows the timing fo r wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction duri ng which the interr upt occurred. in wait mode, the cpu clocks are i nactive. refer to the wait mode subsection of each module to see if th e module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw , in the break system integration module (sim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 89 status register (bsr). if the cop disable bit, co pd, in the mask option register is logic zero , then the computer oper ating properly module (cop) is enabled and remains active in wait mode. figure 7-15. wait mode entry timing figure 7-16 and figure 7-17 show the timing for wait recovery. figure 7-16. wait recovery from interrupt or break figure 7-17. wait recover y from internal reset wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 2oscout 32 cycles 32 cycles system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 90 system integration module (sim) freescale semiconductor 7.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for inte rrupts begins after the selected stop recovery time has elapsed. reset or break al so causes an exit from stop mode. the sim disables the oscillator si gnals (oscout and 2oscout) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the configurati on register (config). if ssrec is set, stop recovery is r educed from the nor mal delay of 4096 2oscout cycles down to 32. this is ideal for applications using canned oscillators that do not require lo ng start-up times from stop mode. note: external crystal applicati ons should use the full stop recovery time by clearing the ssrec bit. a break interrupt during stop mode sets the si m break stop/wait bit (sbsw) in the break st atus register (bsr). the sim counter is held in reset from the execution of the stop instruction until th e beginning of stop recovery. it is then used to time the recovery period. figure 7-18 shows stop mode entry timing. note: to minimize stop current, all pins configured as i nputs should be driven to a logic 1 or logic 0. figure 7-18. stop mode entry timing stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. system integration module (sim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 91 figure 7-19. stop mode recovery from interrupt or break 7.8 sim registers the sim has three memo ry mapped registers. table 7-4 shows the mapping of thes e registers. 7.8.1 break status register (bsr) the break status register contains a flag to indicate that a break caused an exit from stop or wait mode. 2oscout int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period table 7-4. sim registers address register access mode $fe00 bsr user $fe01 rsr user $fe03 bfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a logic zero clears sbsw. figure 7-20. break stat us register (bsr) system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 92 system integration module (sim) freescale semiconductor sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic zero to it. reset clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break state swi r outine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example of this. writing zero to the sbsw bit clears it. 7.8.2 reset status register (rsr) this register contains six flags that show the sour ce of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clear s all other bits in the register. ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,bsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ; if returnlo is not zero, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. system integration module (sim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 93 por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operati ng properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr modrst ? monitor mode entry module reset bit 1 = last reset caused by monitor mode entry when vector locations $fffe and $ffff are $00 after por while irqb = v dd 0 = por or read of srsr lvi ? low voltage i nhibit reset bit 1 = last reset caused by lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 = unimplemented figure 7-21. reset st atus register (rsr) system integration module (sim) technical data mc68h(r)c908jl3 ? rev. 1.1 94 system integration module (sim) freescale semiconductor 7.8.3 break flag control register (bfcr) the break control register contains a bit that enables so ftware to clear status bits while the mc u is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear st atus bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 7-22. break flag control register (bfcr) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor oscillator (osc) 95 technical data ? mc68h(r)c908jl3 section 8. oscillator (osc) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.3 x-tal oscillator (mc68 hc908xxx). . . . . . . . . . . . . . . . . . . . . . . 96 8.4 rc oscillator (mc68hrc9 08xxx) . . . . . . . . . . . . . . . . . . . . . . 97 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 98 8.5.2 crystal amplifier output pi n (osc2/pta6/rcclk) . . . . . . . 98 8.5.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 98 8.5.4 x-tal oscillator clo ck (xtalclk). . . . . . . . . . . . . . . . . . . . .98 8.5.5 rc oscillator clock ( rcclk). . . . . . . . . . . . . . . . . . . . . . . . 99 8.5.6 oscillator out 2 (2oscout ) . . . . . . . . . . . . . . . . . . . . . . . .99 8.5.7 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.7 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.2 introduction the oscillator module provides the reference clock for the mcu system and bus. two types of oscillat or modules are available: mc68hc908xxx? built-in oscillator module (x-tal oscillator) that requires an external crystal or ce ramic-resonator. this option also allows an external cl ock that can be driven directly into osc1. mc68hrc908xxx ? built-in oscillator module (rc oscillator) that requires an external rc connection only. oscillator (osc) technical data mc68h(r)c908jl3 ? rev. 1.1 96 oscillator (osc) freescale semiconductor 8.3 x-tal oscillator (mc68hc908xxx) the x-tal oscillator circuit is designed for use wi th an external crystal or ceramic resonator to provid e accurate clock source. in its typical configurati on, the x-tal oscillator is connected in a pierce oscillator configuration, as shown in figure 8-1 . this figure shows only the logical representat ion of the internal components and may not represent actual circui try. the oscillator conf iguration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) figure 8-1. x-tal oscill ator external connections c 1 c 2 simoscen xtalclk r b x 1 r s * *r s can be zero (shorted) when used with higher-fr equency crystals. mcu from sim refer to manufa cturer?s data. osc2 osc1 2 oscout 2oscout to sim to sim see section 18. for component value requirements. oscillator (osc) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor oscillator (osc) 97 the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all rang es of operation, especially with high frequency cryst als. refer to the crystal manufacturer?s data for more information. 8.4 rc oscillator (mc68hrc908xxx) the rc oscillator circuit is designed for use with external r and c to provide a clock source with tolerance less than 10%. in its typical configur ation, the rc oscillator requires two external components, one r and one c. compo nent values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance. the oscillator conf iguration uses two components: c ext r ext figure 8-2. rc oscillato r external connections mcu r ext c ext simoscen osc1 ext-rc oscillator en rcclk 2 oscout 2oscout to sim from sim v dd pta6 i/o 0 1 pta6 pta6en pta6/rcclk (osc2) to sim see section 18. for component value requirements. oscillator (osc) technical data mc68h(r)c908jl3 ? rev. 1.1 98 oscillator (osc) freescale semiconductor 8.5 i/o signals the following paragraphs describe the oscillator i/o signals. 8.5.1 crystal amplifier input pin (osc1) osc1 pin is an input to the crystal o scillator amplifier or the input to the rc oscillator circuit. 8.5.2 crystal amplifier output pin (osc2/pta6/rcclk) for the x-tal oscillator device , osc2 pin is the out put of the crystal oscillator inverting amplifier. for the rc oscillator dev ice, osc2 pin can be configured as a general purpose i/o pin pta6, or t he output of the internal rc oscillator clock, rcclk. 8.5.3 oscillator enable signal (simoscen) the simoscen signal come s from the system int egration module (sim) and enables/disables the x- tal oscillator circuit or the rc-oscillator. 8.5.4 x-tal oscillator clock (xtalclk) xtalclk is the x-tal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 8-1 shows only the logical relati on of xtalclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of xtalclk is unknown and may depend on the crystal and other external factors. also, the frequ ency and amplitude of xt alclk can be unstable at start-up. option osc2 pin function x-tal oscillator inverting osc1 rc oscillator controlled by ptaen bit in ptapuer ($0d) pta6en = 0: rcclk output pta6en = 1: pta6 i/o oscillator (osc) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor oscillator (osc) 99 8.5.5 rc oscillator clock (rcclk) rcclk is the rc oscill ator output signal. its frequency is directly proportional to t he time constant of t he external r and c. figure 8-2 shows only the logical relation of rcclk to osc1 and may not represent the act ual circuitry. 8.5.6 oscillator out 2 (2oscout) 2oscout is same as the input clo ck (xtalclk or rc clk). this signal is driven to the sim module and is used to determine the cop cycles. 8.5.7 oscillator out (oscout) the frequency of this signal is equal to half of the 2oscou t, this signal is driven to the sim fo r generation of the bus clocks used by the cpu and other modules on the mcu. oscout will be divided again in the sim and results in the in ternal bus frequency being one fourth of the xtalclk or rcclk frequency. 8.6 low power modes the wait and stop in structions put the mcu in low-power consumption standby modes. 8.6.1 wait mode the wait instruction has no effect on the oscilla tor logic. oscout and 2oscout continues to dr ive to the sim module. 8.6.2 stop mode the stop instruction di sables the xtalclk or the rcclk output, hence oscout and 2oscout. oscillator (osc) technical data mc68h(r)c908jl3 ? rev. 1.1 100 oscillator (osc) freescale semiconductor 8.7 oscillator during break mode the oscillator continues to driv e oscout and 2osco ut when the device enters the break state. mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 101 technical data ? mc68h(r)c908jl3 section 9. monitor rom (mon) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 9.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.4.2 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 9.4.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.4 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.4.6 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.2 introduction this section describes the monitor rom (mon) and the monitor mode entry methods. the monitor rom allows complete testing of the mcu through a single-wir e interface with a host com puter. this mode is also used for programming and erasing of flash memory in the mcu. monitor mode entry can be achieved without use of the higher test voltage, v dd +v hi , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardwar e requirements fo r in-circuit programming. monitor rom (mon) technical data mc68h(r)c908jl3 ? rev. 1.1 102 monitor rom (mon) freescale semiconductor 9.3 features features of the monitor rom include the following: normal user-mode pin functionality one pin dedicated to serial co mmunication between monitor rom and host computer standard mark/space non-return -to-zero (nrz) communication with host computer execution of code in ram or flash flash memory security feature 1 flash memory progr amming interface 960 bytes monitor rom code size monitor mode entry wi thout high voltage, v dd +v hi , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode ent ry if high voltage, v dd +v hi , is applied to irq 1 9.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 9-1 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute host-co mputer code in ram while most mcu pins retain norm al operating mode func tions. all communication between the host computer and the m cu is through the ptb0 pin. a level-shifting and multiplexing in terface is required between ptb0 and the host computer. ptb0 is used in a wired-or configuration and requires a pull-up resistor. 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. monitor rom (mon) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 103 figure 9-1. monitor mode circuit + + + + 10m ? mc145407 mc74hc125 hc908jl3 rst irq1 osc1 osc2 v ss ptb0 v dd 10 k ? 10k ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 9.8304mhz 5 6 ptb1 v dd 0.1 f v dd ptb2 v dd 10 k ? ptb3 v dd 10 k ? 10 k ? 10 k ? sw1 a b (see note 1) v dd + v hi sw2 c d (see note 4 and 5) notes: 1. x-tal circuit replaced by rc circuit for mc68hrc908xxx 2. external oscillator mu st have a 50% duty cycle. 3. affects high voltage entry to monitor mode only (sw2 at position c): sw1: position a ? bus clock = osc1 4 sw1: position b ? bus clock = osc1 2 4. sw2: position c ? high voltage entry to monitor mode. input clock = osc1; bus clock depends on sw1. sw2: position d ? bus clock source = x-tal or rc oscillator. bus clock = xtalclk 4 or rcclk 4. 5. see table 18-4 for irq1 voltage level requirements. 10k ? v dd v dd (see note 2) (see note 3) c d c d v dd osc1 osc2 rc circuit (for mc68hrc908xxx) x-tal circuit see figure 18-1 for component values vs. frequency. hc908jk3 hc908jk1 monitor rom (mon) technical data mc68h(r)c908jl3 ? rev. 1.1 104 monitor rom (mon) freescale semiconductor 9.4.1 entering monitor mode table 9-1 shows the pin conditions fo r entering monitor mode. as specified in the table, monitor mode may be ente red after a por and will allow communication at 9600 baud pr ovided one of the fo llowing sets of conditions is met: 1. if irq1 = v dd + v hi : ? external clock on osc1 is 4.9125mhz ? ptb3 = low 2. if irq1 = v dd + v hi : ? external clock on osc1 is 9.8304mhz ? ptb3 = high 3. if $fffe & $ffff is blank (contains $ff): ? the oscillator clock is 9.8304mhz (x-tal or rc) ?irq1 = v dd table 9-1. monitor mode en try requirements and options irq 1 $fffe and $ffff ptb3 ptb2 ptb1 ptb0 clock source and frequency bus frequency comments v dd + v hi x 0011 osc1 at 4.9152mhz 2.4576mhz bypasses x-tal or rc oscillator; external clock driven directly into osc1. 9600 baud communication on ptb0. cop disabled. v dd + v hi x 1011 osc1 at 9.8304mhz 2.4576mhz v dd blank (contain $ff) xxx1 x-tal or rc oscillator at 9.8304mhz 2.4576mhz low-voltage entry to monitor mode. 9600 baud communication on ptb0. cop disabled. v dd not blank xxxx x-tal or rc oscillator at desired frequency xtalclk 4 or rcclk 4 enters user mode. if $fffe and $ffff is blank, mcu will encounter an illegal address reset. notes: 1. ptb3 = 0: bypasses the divide-by -two prescaler to sim when using v dd + v hi for monitor mode entry. the osc1 clock must be 50% duty cycle for this condition. 2. xtalclk is the x-tal oscillator output, for mc68hc908xxx. see figure 8-1 . 4. rcclk is the rc oscillato r output, for mc68hrc908xxx. see figure 8-2 . 5. see table 18-4 for v dd + v hi voltage level requirements. monitor rom (mon) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 105 if v dd +v hi is applied to irq1 and ptb3 is low upo n monitor mode entry ( table 9-1 condition set 1), the bus frequen cy is a divide-by-two of the external clock input to os c1. if ptb3 is high with v dd +v hi applied to irq1 upon monitor mode entry ( table 9-1 condition set 2), the bus frequency is a divide-by-four of the external clock input to osc1. holding the ptb3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if v dd +v hi is applied to irq1 . in this event, the o scout frequency is eq ual to the 2oscout frequency, and osc1 input di rectly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. entering monitor mode with v dd +v hi on irq1 , the cop is disabled as long as v dd +v hi is applied to either the irq1 or the rst . (see section 7. system integr ation module (sim) for more information on modes of operation.) if entering monitor mode without high voltage on irq 1 and reset vector being blank ($fffe and $ffff) ( table 9-1 condition set 3, where applied voltage is v dd ), then all port b pin re quirements and conditions, including the ptb3 frequen cy divisor selection, are not in effect. this is to reduce circuit require ments when performing in -circuit programming. entering monitor mode with the reset vector bei ng blank, the cop is always disabled regardles s of the state of irq1 or the rst . figure 9-2 . shows a simplified diagram of the monitor mode entry when the reset vector is blank and irq1 = v dd . an oscillator frequency (xtalclk or rccclk) of 9.8304mh z is required fo r a baud rate of 9600. monitor rom (mon) technical data mc68h(r)c908jl3 ? rev. 1.1 106 monitor rom (mon) freescale semiconductor figure 9-2. low-voltage mo nitor mode entry flowchart enter monitor mode with the pin co nfiguration shown above by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is la tched, the values on th e specified pins can change. once out of reset, t he mcu waits for the host to send eight security bytes. (see 9.5 security .) after the security bytes, the mcu sends a break signal (10 consecutiv e logic zeros) to the host, indicating that it is ready to receive a command. the br eak signal also pr ovides a timing reference to allow t he host to determine t he necessary baud rate. in monitor mode, the mc u uses different vector s for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. is vector blank? por triggered? normal user mode monitor mode execute monitor code no no yes yes por reset monitor rom (mon) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 107 table 9-2 is a summary of the vector differences between user mode and monitor mode. when the host computer has comple ted downloading code into the mcu ram, the host then sends a run command, whic h executes an rti, which sends control to the address on the stack pointer. 9.4.2 baud rate the communication baud rate is de pendant on oscillator frequency. the state of ptb3 also affects baud rate if entry to monitor mode is by irq1 = v dd +v hi . when ptb3 is high, the divi de by ratio is 1024. if the ptb3 pin is at logic zero up on entry into monitor mode, the divide by ratio is 512. table 9-2. monitor mode vector differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) $fefe $feff $fefc $fefd $fefc $fefd notes: 1. if the high voltage (v dd + v hi ) is removed from the irq 1 pin or the rst pin, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the configuration register. table 9-3. monitor baud rate selection monitor mode entry by: input clock frequency ptb3 baud rate irq1 = v dd + v hi 4.9152 mhz 0 9600 bps 9.8304 mhz 1 9600 bps 4.9152 mhz 1 4800 bps blank reset vector, irq1 = v dd 9.8304 mhz x 9600 bps 4.9152 mhz x 4800 bps monitor rom (mon) technical data mc68h(r)c908jl3 ? rev. 1.1 108 monitor rom (mon) freescale semiconductor 9.4.3 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 9-3 and figure 9-4 .) figure 9-3. monitor data format figure 9-4. sample monitor waveforms the data transmit and receive rate can be anywhere fr om 4800 baud to 28.8k-baud. transmit and receive baud rates must be identical. 9.4.4 echoing as shown in figure 9-5 , the monitor rom immediately echoes each received byte back to the pt b0 pin for error checking. figure 9-5. read transaction any result of a command appears after the ec ho of the last byte of the command. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 addr. high read read addr. high addr. low addr. low data echo sent to monitor result monitor rom (mon) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 109 9.4.5 break signal a start bit followed by nine low bits is a break signal. (see figure 9-6.) when the monitor receives a break sign al, it drives the ptb0 pin high for the duration of tw o bits before echoi ng the break signal. figure 9-6. br eak transaction 9.4.6 commands the monitor rom uses t he following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo monitor rom (mon) technical data mc68h(r)c908jl3 ? rev. 1.1 110 monitor rom (mon) freescale semiconductor table 9-4. read (read memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result table 9-5. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high write write addr. high addr. low addr. low data echo sent to monitor data monitor rom (mon) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 111 note: a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64-kbyte memory map. table 9-6. iread (indexed read) command description read next 2 bytes in me mory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence data iread iread data echo sent to monitor result table 9-7. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence data iwrite iwrite data echo sent to monitor monitor rom (mon) technical data mc68h(r)c908jl3 ? rev. 1.1 112 monitor rom (mon) freescale semiconductor table 9-8. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence sp high readsp readsp sp low echo sent to monitor result table 9-9. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor monitor rom (mon) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 113 9.5 security a security feature discourages unaut horized reading of flash locations while in monitor mode. the host can bypass the securi ty feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locati ons $fff6?$fffd contain user- defined data. note: do not leave locati ons $fff6?$fffd blank . for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send th e eight security bytes on pi n ptb0. if the received bytes match those at location s $fff6?$fffd, the hos t bypasses the security feature and can read al l flash locations and execute code from flash. security remains bypa ssed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. (see figure 9-7 .) figure 9-7. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo ptb0 rst v dd 4096 + 32 oscxclk cycles 24 bus cycles 141 12 1 break notes: 2 = data return delay, 2 bit times 4 = wait 1 bit time before sending next byte. 4 from host from mcu 1 = echo delay, 2 bit times monitor rom (mon) technical data mc68h(r)c908jl3 ? rev. 1.1 114 monitor rom (mon) freescale semiconductor upon power-on reset, if the receiv ed bytes of the se curity code do not match the data at loca tions $fff6?$fffd, the host fails to bypass the security feature. the mcu remain s in monitor mode, but reading a flash location returns an invalid val ue and trying to exec ute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mc u transmits a br eak character, signifying that it is ready to receive a command. note: the mcu does not transmit a break character unti l after the host sends the eight security bytes. to determine whether the security c ode entered is correct, check to see if bit 6 of ram address $ 40 is set. if it is, then the correct security code has been entered and fl ash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to atte mpt another entry. after failing the security s equence, the flash modul e can also be mass erased by executing an erase routine that was downloaded into internal ram. the mass erase operat ion clears the security code locations so that all eight security bytes become $ff (blank). mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 115 technical data ? mc68h(r)c908jl3 section 10. timer interface module (tim) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 120 10.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .120 10.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 121 10.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 122 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 123 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 10.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . . 127 10.10.2 tim counter regist ers (tcnth:tcntl) . . . . . . . . . . . . . . 129 10.10.3 tim counter modul o registers (tmodh:tm odl) . . . . . . 130 10.10.4 tim channel status and co ntrol registers (tsc0:tsc1) . 131 10.10.5 tim channel registers (tch0h /l:tch1h/l) . . . . . . . . . . 135 timer interface module (tim) technical data mc68h(r)c908jl3 ? rev. 1.1 116 timer interface module (tim) freescale semiconductor 10.2 introduction this section describes the timer inte rface module (tim2, version b). the tim is a two-channel time r that provides a timi ng reference with input capture, output compare, and pul se-width-modulation functions. figure 10-1 is a block diagram of the tim. 10.3 features features of the tim include the following: two input capture/ou tput compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input with 7-frequency internal bus clock prescaler selection free-running or modul o up-count operation toggle any channel pin on overflow tim counter stop and reset bits modular architecture expandable to eight channels 10.4 pin name conventions the tim share two i/o pins with two port d i/o pi ns. the full name of the tim i/o pins are listed in table 10-1 . the generic pin name appear in the text that follows. table 10-1. pin name conventions tim generic pin names: tch0 tch1 full tim pin names: ptd4/tch0 ptd5/tch1 timer interface module (tim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 117 10.5 functional description figure 10-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output co mpare functions. the tim counter modulo registers, tmodh:tmodl, contro l the modulo value of the tim counter. software can read th e tim counter value at any time without affecting the counting sequence. the two tim channels are program mable independently as input capture or output compare channels. figure 10-1. tim block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus ms1a internal bus clock tch1 tch0 interrupt logic port logic interrupt logic interrupt logic port logic timer interface module (tim) technical data mc68h(r)c908jl3 ? rev. 1.1 118 timer interface module (tim) freescale semiconductor addr. register name bit 7 6 5 4 3 2 1 bit 0 $0020 tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $0022 tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $0023 tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $0024 tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0025 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0027 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0028 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 figure 10-2. tim i/o register summary timer interface module (tim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 119 10.5.1 tim counter prescaler the tim clock source is one of the seven prescaler outputs. the prescaler generates seven clock rate s from the internal bus clock. the prescaler select bits, ps[2:0], in t he tim status and control register (tsc) select the tim clock source. 10.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an acti ve edge occurs on the pin of an input capture channel, the tim latches the cont ents of the tim counter into the tim channel registers, tc hxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 10.5.3 output compare with the output compare function, the tim can gener ate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the r egisters of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. $0029 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $002a tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset = unimplemented figure 10-2. tim i/o register summary timer interface module (tim) technical data mc68h(r)c908jl3 ? rev. 1.1 120 timer interface module (tim) freescale semiconductor 10.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 10.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt rout ine to write a new, smaller output compare value may caus e the compare to be missed. the tim may pass the new value befor e it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger out put compare value, enable channel x tim overflow interrupts and write the ne w value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter ov erflow period. writing a larger value in an output co mpare interrupt routin e (at the end of the current pulse) could c ause two output compar es to occur in the same counter overflow period. 10.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the lin ked pair alternatel y control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output comp are value in the tim timer interface module (tim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 121 channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enabl es the tim channel 1 registers to synchronously control t he output after the tim overflows. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the output are the ones writte n to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. 10.5.4 pulse width modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 10-3 shows, the output compar e value in the tim channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on outpu t compare if the state of the pwm pulse is logic one. program the tim to set the pin if the state of the pwm pulse is logic zero. timer interface module (tim) technical data mc68h(r)c908jl3 ? rev. 1.1 122 timer interface module (tim) freescale semiconductor figure 10-3. pwm peri od and pulse width the value in the tim counter modu lo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the ti m counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is 000 (see 10.10.1 tim status and control register (tsc) ). the value in the tim chan nel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm sign al is variable in 256 increments. writing $008 0 (128) to the tim c hannel registers produces a duty cycle of 128 /256 or 50%. 10.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 10.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the tim channel registers. an unsynchronized write to the ti m channel registers to change a pulse width value could cause incorrect oper ation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow inte rrupt routine to tchx period pulse width overflow overflow overflow output compare output compare output compare timer interface module (tim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 123 write a new, smaller pulse width value may caus e the compare to be missed. the tim may pass the new value before it is written. use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x tim overflow interrupts a nd write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writin g a larger value in an output compare interrupt routine (at t he end of the curr ent pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 10.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel re gisters of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writ ing to the tim channel 1 registers enables the ti m channel 1 registers to synchronously control the pulse width at t he beginning of the nex t pwm period. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the pulse width are the ones written to last. tsc0 c ontrols and monitors the buffered pwm functi on, and tim channel 1 status and control register timer interface module (tim) technical data mc68h(r)c908jl3 ? rev. 1.1 124 timer interface module (tim) freescale semiconductor (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. writi ng to the acti ve channel registers is the same as gen erating unbuffe red pwm signals. 10.5.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use the follow ing initializat ion procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by se tting the tim stop bit, tstop. b. reset the tim counter by sett ing the tim reset bit, trst. 2. in the tim counter modulo regi sters (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (t chxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered outp ut compare or pwm si gnals) to the mode select bits, msxb:msxa. (see table 10-3 .) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 10-3 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control regist er (tsc), clear t he tim stop bit, tstop. timer interface module (tim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 125 setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tim channel 0 r egisters (tch0h:tch0l) initially control the buffered pwm output. tim status contro l register 0 (tscr0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-ove rflow bit, tovx, inhibi ts output toggles on tim overflows. subsequent outpu t compares try to forc e the output to a state it is already in and have no effect . the result is a 0% duty cycle output. setting the channel x maximum dut y cycle bit (chxm ax) and clearing the tovx bit generates a 100% duty cycle output. (see 10.10.4 tim channel status and control register s (tsc0:tsc1) .) 10.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? th e tof bit is set when the tim counter value rolls over to $0000 after matching t he value in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim stat us and control register. tim channel flags ( ch1f:ch0f) ? the chxf bi t is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxie=1. chxf and chxie ar e in the tim channel x status and control register. 10.7 wait mode the wait instruction puts the mcu in low-power-consumption standby mode. the tim remains active after the executi on of a wait instru ction. in wait mode the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. timer interface module (tim) technical data mc68h(r)c908jl3 ? rev. 1.1 126 timer interface module (tim) freescale semiconductor if tim functions are not required during wait mode, reduce power consumption by stopping the tim befor e executing the wait instruction. 10.8 tim during break interrupts a break interrupt st ops the tim counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the break flag control regi ster (bfcr) enables software to clear status bits during the break state. (see 7.8.3 break flag control register (bfcr) .) to allow software to clear status bi ts during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits dur ing the break state, writ e a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the br eak state without affecting status bits. some status bits have a two- step read/write cleari ng procedure. if software does the first step on such a bit before the brea k, the bit cannot change during the break stat e as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. 10.9 i/o signals port d shares two of its pins with the tim. the two tim channel i/o pins are ptd4/tch0 and ptd5/tch1. each channel i/o pin is progr ammable independently as an input capture pin or an output compare pin. ptd4/tch0 can be configured as a buffered output compare or buffered pwm pin. timer interface module (tim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 127 10.10 i/o registers the following i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim control registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and con trol registers (tsc0 and tsc1) tim channel registers (tch 0h:tch0l and tch1h:tch1l) 10.10.1 tim status and control register (tsc) the tim status and control r egister does the following: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when the tim counter resets to $0000 after reaching the modulo va lue programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and t hen writing a logic zero to tof. if another tim address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 10-4. tim st atus and control register (tsc) timer interface module (tim) technical data mc68h(r)c908jl3 ? rev. 1.1 128 timer interface module (tim) freescale semiconductor overflow occurs before the clear ing sequence is complete, then writing logic zero to tof has no effect. ther efore, a tof interrupt request cannot be lost du e to inadvertent clea ring of tof. reset clears the tof bit. writing a l ogic one to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bi t enables tim overflow in terrupts when the tof bit becomes set. reset cl ears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stop s the tim counter. c ounting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before enteri ng wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tim counter is rese t and always reads as l ogic zero. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tim counter as table 10-2 shows. reset clears the ps[2:0] bits. timer interface module (tim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 129 10.10.2 tim counter registers (tcnth:tcntl) the two read-only tim counter register s contain the high and low bytes of the value in the ti m counter. reading the high byte (tcnth) latches the contents of t he low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tc ntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latc hed during the break. table 10-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 not available timer interface module (tim) technical data mc68h(r)c908jl3 ? rev. 1.1 130 timer interface module (tim) freescale semiconductor 10.10.3 tim counter modulo registers (tmodh:tmodl) the read/write tim modulo registers contain the modul o value for the tim counter. when the tim counter reaches t he modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next clo ck. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim c ounter modulo registers. address: $0021 tcnth bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 address: $0022 tcntl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 = unimplemented figure 10-5. tim counter registers (tcnth:tcntl) timer interface module (tim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 131 note: reset the tim counter bef ore writing to the tim counter modulo registers. 10.10.4 tim channel status and control registers (tsc0:tsc1) each of the tim channel status and control regi sters does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tim overflow selects 100% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation address: $0023 tmodh bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 address: $0024 tmodl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 figure 10-6. tim counter modu lo registers (tmodh:tmodl) timer interface module (tim) technical data mc68h(r)c908jl3 ? rev. 1.1 132 timer interface module (tim) freescale semiconductor chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matche s the value in the ti m channel x registers. when tim cpu interrupt requests are enabled (chxie=1), clear chxf by reading the tim channel x status an d control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effe ct. therefore, an interrupt request cannot be lost due to inadver tent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bi t enables tim cpu interrupt service requests on channel x. reset cl ears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled address: $0025 tsc0 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 address: $0028 tsc1 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 10-7. tim channel status and control registers (tsc0:tsc1) timer interface module (tim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 133 msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to gen eral-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit se lects either input capture operation or unbuffered outp ut compare/pwm operation. see table 10-3 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation when elsxb:a = 00, this read/write bit selects the in itial output level of the tchx pin. (see table 10-3 .) reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to an i/o port, and pin tchx is available as a general-purpose i/o pin. table 10-3 shows how elsxb and elsx a work. reset clears the elsxb and elsxa bits. timer interface module (tim) technical data mc68h(r)c908jl3 ? rev. 1.1 134 timer interface module (tim) freescale semiconductor note: before enabling a tim ch annel register for input capture operation, make sure that the tchx pin is st able for at leas t two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when t he tim counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not t oggle on tim counter overflow. note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic zero, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 10-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. table 10-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 1 output compare or pwm toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare timer interface module (tim) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 135 figure 10-8. chxmax latency 10.10.5 tim channel registers (tch0h/l:tch1h/l) these read/write registers contain the captured tim counter value of the input capture function or the outp ut compare value of the output compare function. the state of the tim channel register s after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tim channel x registers (t chxh) inhibits input c aptures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x regist ers (tchxh) inhibits out put compares until the low byte (tchxl) is written. output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare timer interface module (tim) technical data mc68h(r)c908jl3 ? rev. 1.1 136 timer interface module (tim) freescale semiconductor address: $0026 tch0h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $0027 tch0l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset address: $0029 tch1h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $02a tch1l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset figure 10-9. tim channel regi sters (tch0h/l:tch1h/l) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 137 technical data ? mc68h(r)c908jl3 section 11. analog-to-digital converter (adc) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 11.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 11.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.7.1 adc voltage in ( adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .142 11.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.2 introduction this section describes the analog-to-digital converter (adc). the adc is an 8-bit, 12-channels anal og-to-digital converter. analog-to-digital converter (adc) technical data mc68h(r)c908jl3 ? rev. 1.1 138 analog-to-digital converter (adc) freescale semiconductor 11.3 features features of the ad c module include: 12 channels with multiplexed input linear successive approximation with monotonicity 8-bit resolution single or cont inuous conversion conversion complete flag or conversion complete interrupt selectable adc clock 11.4 functional description twelve adc channels are available for sampling external sources at pins ptb0?ptb7 and ptd0?ptd3. an analog multiplexer allows the single adc converter to select one of the 12 adc channels as adc voltage input (adcvin). adcvin is converted by the successive approximation register-based counter s. the adc resolution is 8 bits. when the conversion is completed, adc puts the result in the adc data register and sets a flag or generates an interrupt. figure 11-2 shows a block diagram of the adc. addr.register name bit 7654321bit 0 $003c adc status and control register (adscr) read: coco aien adco ch4 ch3 ch2 ch1 ch0 write: reset:00011111 $003d adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset $003e adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 figure 11-1. adc i /o register summary analog-to-digital converter (adc) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 139 figure 11-2. adc block diagram 11.4.1 adc port i/o pins ptb0?ptb7 and ptd0?ptd3 are gener al-purpose i/o pins that are shared with the adc channels . the channel select bits (adc status and control register, $003c), define which adc channel/p ort pin will be used as the input signal. the a dc overrides the port i/o logic by forcing that pin as input to the adc. the rema ining adc channel s/port pins are controlled by the port i/o logic and c an be used as general-purpose i/o. internal data bus interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock bus clock ch[4:0] adc data register adiv[2:0] adiclk aien coco disable disable adc channel x read ddrb/ddrd write ddrb/ddrd reset write ptb/ptd read ptb/ptd ddrbx/ddrdx ptbx/ptdx (1 of 12 channels) adcx analog-to-digital converter (adc) technical data mc68h(r)c908jl3 ? rev. 1.1 140 analog-to-digital converter (adc) freescale semiconductor writes to the port register or ddr will not have any affect on the port pin that is selected by the ad c. read of a port pin which is in use by the adc will return a logic 0 if the corresponding ddr bit is at logic 0. if the ddr bit is at logic 1, the value in the port data latch is read. 11.4.2 voltage conversion when the input voltage to the adc equals v dd , the adc converts the signal to $ff (full scale). if the input voltage equals v ss, the adc converts it to $00. i nput voltages between v dd and v ss are a straight-line linear conver sion. all other input volt ages will result in $ff if greater than v dd and $00 if less than v ss . note: input voltage should not exceed the analog supply voltages. 11.4.3 conversion time sixteen adc internal cl ocks are required to perfo rm one conversion. the adc starts a conversion on the first rising edge of the adc internal clock immediately following a wr ite to the adscr. if the adc internal clock is selected to run at 1mhz, t hen one conversion will take 16 s to complete. with a 1mhz adc internal clock t he maximum sample rate is 62.5khz. 11.4.4 continuous conversion in the continuous conv ersion mode, the adc cont inuously converts the selected channel filling t he adc data register wi th new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not . conversions will continue until the adco bit is cleared . the coco bit (adc stat us & control register, $003c) is set after each conversion and can be cleared by writing the adc status and control register or reading of the adc data register. 16 adc clock cycles conversion time = adc clock frequency number of bus cycles = conversion time bus frequency analog-to-digital converter (adc) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 141 11.4.5 accuracy and precision the conversion process is monot onic and has no missing codes. 11.5 interrupts when the aien bit is se t, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 11.6 low-power modes the following subsections describe the adc in lo w-power modes. 11.6.1 wait mode the adc continues norma l operation during wait mode. any enabled cpu interrupt request fro m the adc can bring t he mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting the ch[4:0] bits in the adc status and control register to logic 1?s befor e executing the wa it instruction. 11.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conver sions resume when the mcu exits stop mode. allow one conver sion cycle to stabilize the analog circuitry before attempting a new adc conversion af ter exiting stop mode. 11.7 i/o signals the adc module has 12 channels that are s hared with i/o port b and port d. analog-to-digital converter (adc) technical data mc68h(r)c908jl3 ? rev. 1.1 142 analog-to-digital converter (adc) freescale semiconductor 11.7.1 adc voltage in (adcvin) adcvin is the input volt age signal from one of the 12 adc channels to the adc module. 11.8 i/o registers these i/o registers control and monitor adc operation: adc status and cont rol register (adscr) adc data register (adr) adc clock register (adiclk) 11.8.1 adc status and control register the following paragraphs describe the f unction of the a dc status and control register. coco ? conversions complete bit when the aien bit is a l ogic 0, the coco is a read-only bit which is set each time a conversion is comple ted. this bit is cleared whenever the adc status and contro l register is writt en or whenever the adc data register is read. reset clears this bit. 1 = conversion completed (aien = 0) 0 = conversion not co mpleted (aien = 0) when the aien bit is a logic 1 (cpu interrupt enabled), the coco is a read-only bit, and will always be lo gic 0 when read. address: $003c bit 7654321bit 0 read: coco aien adco ch4 ch3 ch2 ch1 ch0 write: reset:00011111 = unimplemented figure 11-3. adc status and contro l register (adscr) analog-to-digital converter (adc) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 143 aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cl eared when the dat a register is read or the status/control register is written. re set clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert sa mples continuously and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch4, adch3, adch2, adch1, and adch0 fo rm a 5-bit field which is used to select one of the adc channels. the five channel select bits are detailed in the following table. care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. (see table 11-1.) the adc subsystem is turned off w hen the channel select bits are all set to one. this feature allows fo r reduced power consumption for the mcu when the adc is not used. reset sets all of these bits to a logic 1. note: recovery from the disabled stat e requires one conversion cycle to stabilize. analog-to-digital converter (adc) technical data mc68h(r)c908jl3 ? rev. 1.1 144 analog-to-digital converter (adc) freescale semiconductor 11.8.2 adc data register one 8-bit result register is provi ded. this register is updated each time an adc conversion completes. table 11-1. mux channel select ch4 ch3 ch2 ch1 ch0 adc channel input select 00000adc0 ptb0 00001adc1 ptb1 00010adc2 ptb2 00011adc3 ptb3 00100adc4 ptb4 00101adc5 ptb5 00110adc6 ptb6 00111adc7 ptb7 01000adc8 ptd3 01001adc9 ptd2 0 1 0 1 0 adc10 ptd1 0 1 0 1 1 adc11 ptd0 01100 unused (see note 1) ::::: ? 11010 11011 ? reserved 11 1 0 0 ? unused 11 1 0 1 v dda (see note 2) 11 1 1 0 v ssa (see note 2) 11 1 1 1 adc power off notes: 1. if any unused channels are selected, th e resulting adc conversion will be unknown. 2. the voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the adc converter both in pr oduction test and for user applications. analog-to-digital converter (adc) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 145 11.8.3 adc input clock register this register selects the clock frequency for the adc. adiv2:adiv0 ? adc cl ock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit field wh ich selects the divide ratio used by the adc to generat e the internal adc clock. table 11-2 shows the available clock confi gurations. the adc clock should be set to approximately 1mhz. address: $003d bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset = unimplemented figure 11-4. adc data register (adr) address: $003e bit 7654321bit 0 read: adiv2 adiv1 adiv0 00000 write: reset: 0 0000000 = unimplemented figure 11-5. adc input cl ock register (adiclk) analog-to-digital converter (adc) technical data mc68h(r)c908jl3 ? rev. 1.1 146 analog-to-digital converter (adc) freescale semiconductor table 11-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor i/o ports 147 technical data ? mc68h(r)c908jl3 section 12. i/o ports 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.4 port a data register (pta ) . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.4.1 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 150 12.4.2 port a input pull-up enable register (pta pue) . . . . . . . . 151 12.5 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.5.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 153 12.5.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 153 12.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 155 12.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 156 12.6.3 port d control register (pdcr). . . . . . . . . . . . . . . . . . . . . 157 12.2 introduction twenty three bidirectional input-out put (i/o) pins fo rm three parallel ports. all i/o pins are progr ammable as inputs or outputs. note: connect any unused i/o pins to an appr opriate logic level, either v dd or v ss . although the i/o port s do not require te rmination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage. i/o ports technical data mc68h(r)c908jl3 ? rev. 1.1 148 i/o ports freescale semiconductor 12.3 port a port a is an 7-bit special function port that shares all seven of its pins with the keyboard inte rrupt (kbi) module, see section 14. each port a pin also has software configurabl e pull-up device if the corresponding port pin is configured as input port. pta0 to pta5 has direct led drive capability. addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: 0 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: 0 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $000a port d control register (pdcr) read: 0000 slowd7 slowd6 ptdpu7 ptdpu6 write: reset:00000000 $000d port a input pull-up enable register (ptapue) read: pta6en ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 figure 12-1. i/o port register summary i/o ports mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor i/o ports 149 12.4 port a data register (pta) the port a data register (pta) contains a data latch for each of the seven port a pins. pta[6:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. kbi[6:0] ? port a keyboard interrupts the keyboard interrupt enable bits , kbie6-kbie0, in the keyboard interrupt control regist er (kbaier) enable the por t a pins as external interrupt pins, (see section 14. keyboard in terrupt module (kbi) ). address: $0000 bit 7654321bit 0 read: 0 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset additional functions: led (sink) led (sink) led (sink) led (sink) led (sink) led (sink) 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt figure 12-2. port a data register (pta) i/o ports technical data mc68h(r)c908jl3 ? rev. 1.1 150 i/o ports freescale semiconductor 12.4.1 data direction register a (ddra) data direction register a determine s whether each port a pin is an input or an output. writing a l ogic one to a ddra bit enabl es the output buffer for the corresponding port a pin; a logic zero di sables the output buffer. ddra[6:0] ? data dire ction register a bits these read/write bits control port a data direction. reset clears ddra[6:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction regist er a bits fr om 0 to 1. figure 12-4 shows the port a i/o logic. address: $0004 bit 7654321bit 0 read: 0 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 12-3. data dir ection register a (ddra) i/o ports mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor i/o ports 151 figure 12-4. port a i/o circuit when ddrax is a logic 1, readi ng address $0000 reads the ptax data latch. when ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. 12.4.2 port a input pull-up enable register (ptapue) the port a input pull-up enable regist er (ptapue) contains a software configurable pull-up device for each if the seven port a pi ns. each bit is individually configur able and requires the co rresponding data direction register, ddrax be c onfigured as input. ea ch pull-up device is automatically and dynamic ally disabled when its corresponding ddrax bit is configured as output. read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus 30k ptapuex to keyboard interrupt circuit i/o ports technical data mc68h(r)c908jl3 ? rev. 1.1 152 i/o ports freescale semiconductor pta6en ? enable pta6 on osc2 this read/write bit c onfigures the osc2 pin function when rc oscillator option is selected. this bit has no ef fect for x-tal oscillator option. 1 = osc2 pin configured for pta6 i/ o, and has all t he interrupt and pull-up functions. 0 = osc2 pin outputs the rc oscillator clock (rcclk) ptapue[6:0] ? port a in put pull-up enable bits these read/write bits are software program mable to enable pull-up devices on port a pins 1 = corresponding port a pin configured to have internal pull if its ddra bit is set to 0 0 = pull-up device is disconnecte d on the corres ponding port a pin regardless of the st ate of its ddra bit. table 12-1 summarizes the operati on of the port b pins. address: $000d bit 7654321bit 0 read: pta6en ptapue 6 ptapue 5 ptapue 4 ptapue 3 ptapue 2 ptapue 2 ptapue 0 write: reset:00000000 figure 12-5. port a input pull -up enable regi ster (ptapue) table 12-1. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 10x (1) input, v dd (2) ddra6-ddra0 pin pta6-pta0 (3) 0 0 x input, hi-z (4) ddra6-ddra0 pin pta6-pta0 (3) x 1 x output ddra6-ddra0 pta6-pta0 pta6-pta0 1. x = don?t care. 2. i/o pin pulled to v dd by internal pull-up. 3. writing affects data register, but does not affect input. 4. hi-z = high impedence i/o ports mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor i/o ports 153 12.5 port b port b is an 8-bit special function port th at shares all eight of its port pins with the analog-to-digital converter (adc) module, see section 11. 12.5.1 port b data register (ptb) the port b data register co ntains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. 12.5.2 data direction register b (ddrb) data direction register b determine s whether each port b pin is an input or an output. writing a l ogic one to a ddrb bit enabl es the output buffer for the corresponding port b pin; a logic zero di sables the output buffer. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative function: adc7 adc6 adc5 adc4 adc3 adc2 adc2 adc0 figure 12-6. port b data register (ptb) address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 12-7. data dir ection register b (ddrb) i/o ports technical data mc68h(r)c908jl3 ? rev. 1.1 154 i/o ports freescale semiconductor ddrb[7:0] ? data dire ction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pi ns by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 12-8 shows the port b i/o logic. figure 12-8. port b i/o circuit when ddrbx is a logic 1, reading address $0001 reads the hotbox data latch. when ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 12-2 summarizes the operation of the port b pins. table 12-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb7-ddrb0 pin ptb[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrb7-ddrb0 pin ptb[7:0] read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus to analog-to-digital converter i/o ports mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor i/o ports 155 12.6 port d port d is an 8-bit special function port that shares two of its pins with timer interface module, (see section 10. ) and shares four of its pins with analog to digital conversion module (see section 11. ). ptd6 and ptd7 each has high cu rrent drive (25ma sink ) and programmable pull- up. ptd2, ptd3, ptd6 and ptd7 ea ch has led driving capability. 12.6.1 port d data register (ptd) the port d data register c ontains a data latch for each of the eight port d pins. ptd[7:0] ? port d data bits these read/write bits are software programmable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: additional functions led led led led adc8 adc9 adc10 adc11 tch1 tch0 25ma sink (slow edge) 25ma sink (slow edge) 5k pull-up 5k pull-up figure 12-9. port d data register (ptd) i/o ports technical data mc68h(r)c908jl3 ? rev. 1.1 156 i/o ports freescale semiconductor 12.6.2 data direction register d (ddrd) data direction register d determines whether eac h port d pin is an input or an output. writing a logic one to a ddrd bit enables the output buffer for the corresponding port d pin; a logic zero di sables the output buffer. ddrd[7:0] ? data dire ction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writ ing to the port d dat a register before changing data direction register d bits from 0 to 1. figure 12-11 shows the port d i/o logic. figure 12-11. port d i/o circuit address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 12-10. data dir ection register d (ddrd) read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus ptd[0:3] to analog-to-digital converte r 5k ptdpu[6:7] ptd[4:5] to timer i/o ports mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor i/o ports 157 when ddrdx is a logic 1, reading address $0003 reads the ptdx data latch. when ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 12-3 summarizes the operation of the port d pins. 12.6.3 port d control register (pdcr) the port d control register enables /disables the pull-up resistor and slow-edge high current capability of pins ptd6 and ptd7. slowdx ? slow edge enable the slowd6 and slowd7 bits enabl e the slow-edge, open-drain, high current output (25ma sink) of port pins ptd6 and ptd7 respectively. ddrx bit is not affected by slowdx. 1 = slow edge enabled; pin is open-drain output 0 = slow edge disabled; pin is push-pull ptdpux ? pull-up enable the ptdpu6 and ptdpu7 bits enable the 5k pull-up on ptd6 and ptd7 respectively, regardle ss the status of ddrdx bit. 1 = enable 5k pull-up 0 = disable 5k pull-up table 12-3. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddra accesses to ptd read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrd[7:0] pin ptd[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrd[7:0] pin ptd[7:0] address: $000a bit 7654321bit 0 read: 0000 slowd7 slowd6 ptdpu7 ptdpu6 write: reset:00000000 figure 12-12. port d co ntrol register (pdcr) i/o ports technical data mc68h(r)c908jl3 ? rev. 1.1 158 i/o ports freescale semiconductor mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 159 technical data ? mc68h(r)c908jl3 section 13. external interrupt (irq) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 13.4.1 irq1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 163 13.6 irq status and control register (iscr) . . . . . . . . . . . . . . . . 163 13.2 introduction the irq (external interrupt) module pr ovides a maskable interrupt input. 13.3 features features of the irq modul e include the following: a dedicated external interrupt pin, i rq1 irq1 interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge selectable internal pullup resistor external interrupt (irq) technical data mc68h(r)c908jl3 ? rev. 1.1 160 external interrupt (irq) freescale semiconductor 13.4 functional description a logic zero applied to th e external interrupt pin can latch a cpu interrupt request. figure 13-1 shows the structure of the irq module. interrupt signals on the irq1 pin are latched into the irq1 latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clea r the interrupt latch by writing to the acknowledge bit in the inte rrupt status and control register (iscr). writing a logic one to the ack1 bit cl ears the irq1 latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is fal ling-edge-triggered and is software- configurable to be either falli ng-edge or falling-edge and low-level- triggered. the mode1 bit in the iscr controls th e triggering sensitivity of the irq1 pin. when the interrupt pin is edge-trigger ed only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both fallin g-edge and low-leve l-triggered, the cpu interrupt request remains set unt il both of the following occur: vector fetch or software clear return of the interr upt pin to logic one the vector fetch or software clear ma y occur before or af ter the interrupt pin returns to logic one. as long as the pin is lo w, the interrupt request remains pending. a reset will clear th e latch and the mode1 control bit, thereby clearing the interrup t even if the pin stays low. when set, the imask1 bi t in the iscr mask al l external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask1 bit is clear. external interrupt (irq) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 161 note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including external interrupt requests. (see 7.6 exception control .) figure 13-1. irq module block diagram 13.4.1 irq1 pin a logic zero on the irq1 pin can latch an interrup t request into the irq1 latch. a vector fetch, software cl ear, or reset clears the irq1 latch. if the mode1 bit is set, the irq1 pin is both falling-edge-sensitive and low-level-sensitive. with mode1 set, both of the follow ing actions must occur to clear irq1: ack1 imask1 dq ck clr irq1 high interrupt to mode select logic irq1 ff request v dd mode1 voltage detect synchro- nizer irqf1 to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd i nternal pullup device irq1 irqpud addr.register name bit 7654321bit 0 $001d irq status and control register (intscr) read: 0000irqf10 imask1 mode1 write: ack1 reset:00000000 = unimplemented figure 13-2. irq i/o register summary external interrupt (irq) technical data mc68h(r)c908jl3 ? rev. 1.1 162 external interrupt (irq) freescale semiconductor vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to cl ear the latch. software may generate the interrupt acknowledge sig nal by writing a logic one to the ack1 bit in the in terrupt status and cont rol register (iscr). the ack1 bit is useful in app lications that poll the irq1 pin and require software to clear the irq1 latch. writing to the ack1 bit prior to leaving an interrupt se rvice routine can also prevent spurious interrupts due to noise . setting ack1 d oes not affect subsequent transitions on the irq1 pin. a falling edge that occurs after writing to the ack1 bit latc hes another interr upt request. if the irq1 mask bit, imask1, is clear, the cpu loads the program counter with t he vector address at lo cations $fffa and $fffb. return of the irq1 pin to logic one ? as long as the irq1 pin is at logic zero, irq1 remains active. the vector fetch or software cl ear and the return of the irq1 pin to logic one may occur in any or der. the interrupt reques t remains pending as long as the irq1 pin is at logic zero. a rese t will clear the latch and the mode1 control bit, thereby clearing the interrupt even if the pin stays low. if the mode1 bit is clear, the irq1 pin is falling-edge-s ensitive only. with mode1 clear, a vector fe tch or software clear immediately clears the irq1 latch. the irqf1 bit in the iscr register can be used to check for pending interrupts. the irqf1 bit is not affe cted by the imask1 bit, which makes it useful in applications where polling is preferred. use the bih or bil in struction to read the logic level on the irq1 pin. note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine. note: an internal pull-up resistor to v dd is connected to the irq1 pin; this can be disabled by setting the irqpud bit in the conf ig2 register ($001e). external interrupt (irq) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 163 13.5 irq module during break interrupts the system integration module (sim) c ontrols whether the irq1 latch can be cleared during the br eak state. the bcfe bi t in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 7. system inte gration module (sim) .) to allow software to clear the irq1 latch during a break interrupt, write a logic one to the bcfe bit. if a latc h is cleared during the break state, it remains cleared when the m cu exits the break state. to protect the latches during the break state, write a l ogic zero to the bcfe bit. with bcfe at logic zero (i ts default state), writing to the ack1 bit in the irq status and control regi ster during the br eak state has no effect on the irq latch. 13.6 irq status and co ntrol register (iscr) the irq status and control register (iscr) controls and monitors operation of the irq m odule. the iscr has the following functions: shows the state of the irq1 flag clears the irq1 latch masks irq1 and interrupt request controls triggering se nsitivity of the irq1 interrupt pin address: $001d bit 7654321bit 0 read: 0000irqf1 imask1 mode1 write: ack1 reset:00000000 = unimplemented figure 13-3. irq status and control register (intscr) external interrupt (irq) technical data mc68h(r)c908jl3 ? rev. 1.1 164 external interrupt (irq) freescale semiconductor irqf1 ? irq1 flag this read-only status bi t is high when the irq1 interrupt is pending. 1 = irq1 interrupt pending 0 = irq1 interrupt not pending ack1 ? irq1 interrupt request acknowledge bit writing a logic one to this write-onl y bit clears the irq1 latch. ack1 always reads as logic ze ro. reset cl ears ack1. imask1 ? irq1 interrupt mask bit writing a logic one to th is read/write bit dis ables irq1 interrupt requests. reset clears imask1. 1 = irq1 interrupt requests disabled 0 = irq1 interrupt requests enabled mode1 ? irq1 edge/level select bit this read/write bit cont rols the triggering se nsitivity of the irq1 pin. reset clears mode1. 1 = irq1 interrupt requests on falling edges and low levels 0 = irq1 interrupt requests on falling edges only irqpud ? irq1 pin pull-up control bit 1 = internal pull- up is disconnected 0 = internal pull-up is connec ted between irq1 pin and v dd address: $001e bit 7654321bit 0 read: irqpud r r lvit1 lvit0 r r r write: reset:000 not affected not affected 000 por:00000000 r=reserved figure 13-4. configurati on register 2 (config2) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 165 technical data ? mc68h(r)c908jl3 section 14. keyboard interrupt module (kbi) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 14.4.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.4.2 keyboard status and control register. . . . . . . . . . . . . . . . 169 14.4.3 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 170 14.5 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.6 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.7 keyboard module during break interrupts . . . . . . . . . . . . . . . 171 14.2 introduction the keyboard interrupt module (kbi ) provides seven independently maskable external interrupts whic h are accessible vi a pta0?pta6 pins. 14.3 features features of the keyboard interr upt module inclu de the following: seven keyboard interrupt pins with separate keyboard interrupt enable bits and one keyb oard interrupt mask software configurable pull-up devic e if input pin is configured as input port bit programmable edge-only or edge- and level- interrupt sensitivity exit from low-power modes keyboard interrupt module (kbi) technical data mc68h(r)c908jl3 ? rev. 1.1 166 keyboard interrupt module (kbi) freescale semiconductor 14.4 functional description figure 14-2. keyboard in terrupt block diagram writing to the kbie6?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pin. enabling a keyboard interrupt pin in port a also enables its internal pull-up device irrespective of ptapuex bits in the port a input pull-up enable register (see 12.4.2 ). a logic 0 appli ed to an enabled keyboard interrupt pin latches a keyboard interrupt request. addr.register name bit 7654321bit 0 $001a keyboard status and control register (kbscr) read:0000 keyf 0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) read: 0 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 14-1. kbi i/o register summary kbie0 kbie6 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbi6 kbi0 synchronizer keyf keyboard interrupt request to pullup enable to pullup enable keyboard interrupt module (kbi) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 167 a keyboard interrupt is latched w hen one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is e dge-sensitive only, a falling edge on a keyboard pin does not latch an in terrupt reques t if another keyboard pin is already low. to pr event losing an interrupt request on one pin because another pin is still low, software can disable the latter pin wh ile it is low. if the keyboard interrupt is falli ng edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins ar e both falling edge- and low level-sensitive, and both of t he following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowle dge signal by writing a logic 1 to t he ackk bit in the keyboa rd status and control register kbscr. the ackk bit is useful in app lications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can al so prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bi t latches another inte rrupt request. if the keyboard interrupt mask bit, imask k, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. return of all enabled keyboard interr upt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. keyboard interrupt module (kbi) technical data mc68h(r)c908jl3 ? rev. 1.1 168 keyboard interrupt module (kbi) freescale semiconductor if the modek bit is clear, the key board interrupt pin is falling-edge- sensitive only. with mo dek clear, a vector fetc h or software clear immediately clears the ke yboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the ke yboard status and control register can be used to see if a pending inte rrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications wh ere polling is preferred. to determine the logic level on a key board interrupt pin, disable the pull- up device, use the data direction regist er to configure t he pin as an input and then read the data register. note: setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an inpu t, overriding t he data direction register. however, the dat a direction register bi t must be a logic 0 for software to read the pin. 14.4.1 keyboard initialization when a keyboard interrupt pin is enabl ed, it takes time for the internal pull-up to reach a logic 1. therefor e a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by se tting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and keyboard interrupt module (kbi) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 169 level-triggered interrupt pin must be acknowledged afte r a delay that depends on the external load. another way to avoi d a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddra bits in the data direction register a. 2. write logic 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 14.4.2 keyboard status and control register flags keyboard interrupt requests. acknowledges keyboard interrupt requests. masks keyboard interrupt requests. controls keyboard interrupt triggering sensitivity. bits 7?4 ? not used these read-only bits alwa ys read as logic 0s. keyf ? keyboard flag bit this read-only bit is set when a keyb oard interrupt is pending on port- a. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending address: $001a bit 7654321bit 0 read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 = unimplemented figure 14-3. keyboard status and control regi ster (kbscr) keyboard interrupt module (kbi) technical data mc68h(r)c908jl3 ? rev. 1.1 170 keyboard interrupt module (kbi) freescale semiconductor ackk ? keyboard acknowledge bit writing a logic 1 to th is write-only bit clears the keyboard interrupt request on port-a. ackk al ways reads as logic 0. reset clears ackk. imaskk? keyboard interrupt mask bit writing a logic 1 to th is read/write bit prev ents the output of the keyboard interrupt mask from generati ng interrupt requests on port-a. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard tri ggering sensitivity bit this read/write bit controls the tri ggering sensitivity of the keyboard interrupt pins on port-a. reset clears modek. 1 = keyboard interrupt reques ts on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 14.4.3 keyboard interrupt enable register the port-a keyboard interrupt enable register enables or disables each port-a pin to operate as a keyboard interrupt pin. kbie6?kbie0 ? port-a key board interrupt enable bits each of these read/write bits enables the corres ponding keyboard interrupt pin on port-a to latch inte rrupt requests. reset clears the keyboard interrupt enable register. 1 = kbix pin enabled as keyboard interrupt pin 0 = kbix pin not enabled as keyboar d interrupt pin address: $001b bit 7654321bit 0 read: 0 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 14-4. keyboard interr upt enable register (kbier) keyboard interrupt module (kbi) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 171 14.5 wait mode the keyboard modules remain active in wait mode. clearing the imaskk bit in the keyboar d status and control r egister enables keyboard interrupt requests to brin g the mcu out of wait mode. 14.6 stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboar d status and control r egister enables keyboard interrupt requests to bring the mcu out of stop mode. 14.7 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during t he break state. the bcfe bit in the break flag control register (bfcr) enabl es software to clear status bits during the break state. to allow software to clear the key board interrupt la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared w hen the mcu exits the break state. to protect the latch during the break st ate, write a logi c 0 to the bcfe bit. with bcfe at logi c 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect. keyboard interrupt module (kbi) technical data mc68h(r)c908jl3 ? rev. 1.1 172 keyboard interrupt module (kbi) freescale semiconductor mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 173 technical data ? mc68h(r)c908jl3 section 15. computer operating properly (cop) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 15.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.1 2oscout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15.4.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15.4.3 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.5 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.4.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.4.7 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 176 15.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 15.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 178 15.2 introduction the computer operating properly (cop ) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runa way code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the config1 register. computer operating properly (cop) technical data mc68h(r)c908jl3 ? rev. 1.1 174 computer operating properly (cop) freescale semiconductor 15.3 functional description figure 15-1 shows the structure of the cop module. figure 15-1. cop block diagram the cop counter is a fr ee-running 6-bit counter preceded by the 12-bit system integration module (sim) counter. if not cl eared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 or 2 13 ?2 4 2oscout cycles; depending on the state of the cop rate select bit, coprs, in c onfiguration register 1. with a 2 18 ?2 4 2oscout cycle overflow option, a 8m hz crystal give s a cop timeout period of 32.766 ms. writing any value to location $ffff before an overflow occurs prevents a cop re set by clearing the cop counter and stages 12 through 5 of the sim counter. copctl write 2oscout reset vector fetch sim reset circuit reset status register internal reset sources (1) sim clear stages 5?12 12-bit sim counter clear all stages copd (from config1) reset copctl write clear cop module copen (from sim) cop counter note: 1. see sim section for more details. cop clock cop timeout cop rate sel (coprs from config1) 6-bit cop counter computer operating properly (cop) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 175 note: service the cop immediately after re set and before entering or after exiting stop mode to guarantee the ma ximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 2oscout cycles and sets the cop bit in the reset st atus register (rsr). (see 7.8.2 reset status register (rsr) .). note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 15.4 i/o signals the following paragraphs descri be the signals shown in figure 15-1 . 15.4.1 2oscout 2oscout is the oscillator output signal. 2oscout frequency is equal to the crystal fr equency or the rc-o scillator frequency. 15.4.2 copctl write writing any value to the cop control register (copctl) (see 15.5 cop control register ) clears the cop counter a nd clears bits 12 through 5 of the sim counter. readi ng the cop control register returns the low byte of the reset vector. 15.4.3 power-on reset the power-on reset (por) circuit in the sim clears the sim counter 4096 2oscout cycles after power-up. 15.4.4 internal reset an internal reset clears the sim counter and the cop counter. computer operating properly (cop) technical data mc68h(r)c908jl3 ? rev. 1.1 176 computer operating properly (cop) freescale semiconductor 15.4.5 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the sim counter. 15.4.6 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the configuration regist er (config). (see section 5. configuration register (config) .) 15.4.7 coprs (cop rate select) the coprs signal reflects the state of the cop ra te select bit (coprs) in the configuration register 1. coprs ? cop rate select bit coprs selects the cop timeout period. rese t clears coprs. 1 = cop timeout period is (2 13 ? 2 4 ) 2oscout cycles 0 = cop timeout period is (2 18 ? 2 4 ) 2oscout cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: coprs r r lvid r ssrec stop copd write: reset:00000000 r=reserved figure 15-2. configurati on register 1 (config1) computer operating properly (cop) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 177 15.5 cop control register the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. 15.6 interrupts the cop does not generate cpu interrupt requests. 15.7 monitor mode the cop is disabled in monitor mode when v dd +v hi is present on the irq1 pin or on the rst pin. 15.8 low-power modes the wait and stop in structions put the mcu in low-power consumption standby modes. 15.8.1 wait mode the cop continues to operate duri ng wait mode. to prevent a cop reset during wait mode, periodicall y clear the cop counter in a cpu interrupt routine. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 15-3. cop cont rol register (copctl) computer operating properly (cop) technical data mc68h(r)c908jl3 ? rev. 1.1 178 computer operating properly (cop) freescale semiconductor 15.8.2 stop mode stop mode turns off the 2oscout i nput to the cop and clears the sim counter. service the cop immediatel y before entering or after exiting stop mode to ensure a full cop timeout period a fter entering or exiting stop mode. 15.9 cop module during break mode the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor low voltage inhibit (lvi) 179 technical data ? mc68h(r)c908jl3 section 16. low voltage inhibit (lvi) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 16.5 lvi control register (config2/con fig1) . . . . . . . . . . . . . . 180 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 16.2 introduction this section describes the low-vo ltage inhibit module (lvi), which monitors the vo ltage on the v dd pin and generates a reset when the v dd voltage falls to the lvi trip (lvi trip ) voltage. 16.3 features features of the lvi modu le include the following: selectable lvi trip voltage selectable lvi circuit disable low voltage inhibit (lvi) technical data mc68h(r)c908jl3 ? rev. 1.1 180 low voltage inhibit (lvi) freescale semiconductor 16.4 functional description figure 16-1 shows the structur e of the lvi module. the lvi is enabled after a reset. the lvi module cont ains a bandgap refe rence circuit and comparator. setting lvi di sable bit (lvid) disables the lvi to monitor v dd voltage. the lvi trip voltage selection bits (lvit1, lvit0) determines at which v dd level the lvi module should take actions. the lvi module generates one output signal: lvi reset ? an reset signal w ill be generated to reset the cpu when v dd drops to below t he set trip point. figure 16-1. lvi module block diagram 16.5 lvi control register (config2/config1) low v dd lv t 1 lv i d detector v dd lvi reset lv t 0 v dd > lvi trip = 0 v dd < lvi trip = 1 address: $001e bit 7654321bit 0 read: irqpud r r lvit1 lvit0 r r r write: reset:000 not affected not affected 000 por:00000000 r= reserved figure 16-2. configurati on register 2 (config2) low voltage inhibit (lvi) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor low voltage inhibit (lvi) 181 lvid ?tlow voltage inhibit disable bit 1 = low voltage inhibit disabled 0 = low voltage inhibit enabled lvit1, lvit0 ? lvi tr ip voltage selection these two bits determine at which level of v dd the lvi module will come into action. lvi t1 and lvit0 are cleared by a power-on reset only. 16.6 low-power modes the stop and wait instructions put the mcu in low-power- consumption standby modes. 16.6.1 wait mode the lvi module, when enabl ed, will continue to op erate in wait mode. 16.6.2 stop mode the lvi module, when enabl ed, will continue to op erate in stop mode. address: $001f bit 7654321bit 0 read: coprs r r lvid r ssrec stop copd write: reset:00000000 r=reserved figure 16-3. configurati on register 1 (config1) lvit1 lvit0 trip voltage (1) 1. see section 18. electrical specifications for full parameters. comments 00v lv r 3 (2.4v) for v dd =3v operation 01v lv r 3 (2.4v) for v dd =3v operation 10v lv r 5 (4.0v) for v dd =5v operation 11reserved low voltage inhibit (lvi) technical data mc68h(r)c908jl3 ? rev. 1.1 182 low voltage inhibit (lvi) freescale semiconductor mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconducto r break module (break) 183 technical data ? mc68h(r)c908jl3 section 17. break module (break) 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 17.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 186 17.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .186 17.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 186 17.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 186 17.5 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 17.5.1 break status and control regist er (brkscr) . . . . . . . . . 187 17.5.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 188 17.5.3 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 17.5.4 break flag control register (bfcr) . . . . . . . . . . . . . . . . . 190 17.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 17.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 17.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 17.2 introduction this section describes the break module. the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. break module (break) technical data mc68h(r)c908jl3 ? rev. 1.1 184 break module (break) fr eescale semiconductor 17.3 features features of the break m odule include the following: accessible i/o registers during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 17.4 functional description when the internal address bus matches the value written in the break address registers, the br eak module issues a breakpoint signal (bkpt ) to the sim. the sim then causes the cpu to load t he instruction register with a software interrupt instruction (swi) after completi on of the current cpu instruction. the program coun ter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the addr ess in the program counter) matches the contents of th e break address registers. software writes a logic one to t he brka bit in the break status and control register. when a cpu generated addre ss matches the contents of the break address registers, th e break interrupt begins af ter the cpu completes its current instruction. a return from in terrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 17-1 shows the structure of the break module. break module (break) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconducto r break module (break) 185 figure 17-1. break module block diagram iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] bkpt (to sim) addr.register name bit 7654321bit 0 $fe00 break status register (bsr) read: rrrrrr sbsw r write: see note reset: 0 $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address high register (brkh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0d break address low register (brkl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 17-2. break i/ o register summary break module (break) technical data mc68h(r)c908jl3 ? rev. 1.1 186 break module (break) fr eescale semiconductor 17.4.1 flag protection during break interrupts the system integration module (sim) controls whether or not module status bits can be clea red during the break stat e. the bcfe bit in the break flag control register (bfcr) enabl es software to clear status bits during the break state. (see 7.8.3 break flag cont rol register (bfcr) and see the break interrupts subsection for each module.) 17.4.2 cpu during break interrupts the cpu starts a br eak interrupt by: loading the instruction regist er with the swi instruction loading the program counter wi th $fffc:$fffd ($fefc:$fefd in monitor mode) the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 17.4.3 tim during break interrupts a break interrupt stops the timer counter. 17.4.4 cop during break interrupts the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. 17.5 break module registers these registers control and monitor operation of the break module: break status and cont rol register (brkscr) break address regi ster high (brkh) break address regi ster low (brkl) break status register (bsr) break flag contro l register (bfcr) break module (break) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconducto r break module (break) 187 17.5.1 break status and control register (brkscr) the break status and control register contains break module enable and status bits. brke ? break enable bit this read/write bit enabl es breaks on break address register matches. clear brke by writing a logic zero to bit 7. reset clears the brke bit. 1 = breaks enabled on 16 -bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is se t when a break address match occurs. writing a logic one to brka generates a break interrupt. clear brka by writing a logic zero to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 17-3. break status an d control register (brkscr) break module (break) technical data mc68h(r)c908jl3 ? rev. 1.1 188 break module (break) fr eescale semiconductor 17.5.2 break address registers the break address registers contai n the high and low bytes of the desired breakpoint address. reset cl ears the break ad dress registers. 17.5.3 break status register the break status register contains a flag to indicate that a break caused an exit from stop or wait mode. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 17-4. break addres s register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 17-5. break address regist er low (brkl) address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a logic zero clears sbsw. figure 17-6. break stat us register (bsr) break module (break) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconducto r break module (break) 189 sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic zero to it. reset clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break state swi r outine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example of this. writing zero to the sbsw bit clears it. ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,bsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ; if returnlo is not zero, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. break module (break) technical data mc68h(r)c908jl3 ? rev. 1.1 190 break module (break) fr eescale semiconductor 17.5.4 break flag control register (bfcr) the break control register contains a bit that enables so ftware to clear status bits while the mc u is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear st atus bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break 17.6 low-power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 17.6.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the re turn address on the stack if sbsw is set (see 7.7 low-power modes ). clear the sbsw bi t by writing logic zero to it. 17.6.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. see 7.8 sim registers . address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 17-7. break flag control register (bfcr) mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor electrical specifications 191 technical data ? mc68h(r)c908jl3 section 18. electrical specifications 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 18.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.6 5v dc electrical characte ristics. . . . . . . . . . . . . . . . . . . . . . . 194 18.7 5v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 18.8 5v oscillator charac teristics. . . . . . . . . . . . . . . . . . . . . . . . . . 196 18.9 3v dc electrical characte ristics. . . . . . . . . . . . . . . . . . . . . . . 197 18.10 3v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 18.11 3v oscillator characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 199 18.12 typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 18.13 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18.14 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 18.2 introduction this section contains electrical and timing specifications. electrical specifications technical data mc68h(r)c908jl3 ? rev. 1.1 192 electrical specifications freescale semiconductor 18.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. note: this device is not guar anteed to operate properly at the maximum ratings. refer to sections 18.6 and 18.9 for guaranteed operating conditions. note: this device contains circ uitry to protect the i nputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applic ation of any voltage higher than maximum-rated voltages to this hi gh-impedance circui t. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are co nnected to an appropriate logic voltage level (for example, either v ss or v dd .) table 18-1. absolute maximum ratings (1) characteristic symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v mode entry voltage, i rq1 pin v dd +v hi v ss ?0.3 to +8.5 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma note: 1. voltages referenced to v ss . electrical specifications mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor electrical specifications 193 18.4 functional operating range 18.5 thermal characteristics table 18-2. operating range characteristic symbol value unit operating temperature range t a ? 40 to +125 ? 40 to +85 c operating voltage range v dd 5v 1 0% 3v 10% v table 18-3. thermal characteristics characteristic symbol value unit thermal resistance 20-pin pdip 20-pin soic 28-pin pdip 28-pin soic ja 70 70 70 70 c/w c/w c/w c/w i/o pin power dissipation p i/o user determined w power dissipation (1) p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c) w constant (2) k p d x (t a + 273 c ) + p d 2 ja w/ c average junction temperature t j t a + (p d ja ) c maximum junction temperature t jm 100 c notes: 1. power dissipation is a function of temperature. 2. k constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . electrical specifications technical data mc68h(r)c908jl3 ? rev. 1.1 194 electrical specifications freescale semiconductor 18.6 5v dc electrical characteristics table 18-4. dc electri cal characteristics (5v) characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?2.0ma) pta0?pta6, ptb0?ptb7, ptd0?ptd7 v oh v dd ?0.8 ??v output low voltage (i load = 1.6ma) pta6, ptb0?ptb7, ptd0, ptd1, ptd4, ptd5 v ol ??0.4v output low voltage (i load = 25ma) ptd6, ptd7 v ol ??0.5v led drives (v ol = 3v) pta0?pta5, ptd2, ptd3, ptd6, ptd7 i ol 10 19 25 ma input high voltage pta0?pta6, ptb0?ptb7, ptd0?ptd7, r st , irq 1 , osc1 v ih 0.7 v dd ? v dd v input low voltage pta0?pta6, ptb0?ptb7, ptd0?ptd7, rst , irq 1 , osc1 v il v ss ? 0.3 v dd v v dd supply current run, f op = 4mhz (3) wait (mc68hrc908xxx) (4) wait (mc68hc908xxx) (4) stop (5) ?40 c to 85 c i dd ? ? ? ? 7 1 5 1 10 1.5 5.5 5 ma ma ma a digital i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (6) v por 0?100mv por rise time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v dd +v hi 1.5 v dd ? 8.5 v pullup resistors (8) ptd6, ptd7 rst , irq1 , pta0?pta6 r pu1 r pu2 1.8 16 3.3 26 4.8 36 k ? k ? lv i r e s e t vo l t a g e v lv r 5 3.6 4.0 4.4 v electrical specifications mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor electrical specifications 195 18.7 5v control timing notes: 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source . all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f op = 4mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; all ports configured as inputs; osc2 capacitance linearly af- fects wait i dd . 5. stop i dd measured with osc1 grounded, no port pins sourcing current. lvi is disabled. 6. maximum is highest voltage that por is guaranteed. 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 8. r pu1 and r pu2 are measured at v dd = 5.0v table 18-5. control timing (5v) characteristic (1) notes: 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v ss , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor- mation. f op ?8mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 750 ? ns table 18-4. dc electri cal characteristics (5v) characteristic (1) symbol min typ (2) max unit electrical specifications technical data mc68h(r)c908jl3 ? rev. 1.1 196 electrical specifications freescale semiconductor 18.8 5v oscillator characteristics figure 18-1. rc vs . frequency (5v @25 c) table 18-6. oscillator component specifications (5v) characteristic symbol min typ max unit crystal frequency, xtalclk f oscxclk ?10 32 mhz rc oscillator frequency, rcclk f rcclk 210 12 mhz external clock reference frequency (1) f oscxclk dc ? 32 mhz crystal load capacitance (2) c l ?? ? crystal fixed capacitance (2) c 1 ? 2 c l ? crystal tuning capacitance (2) c 2 ? 2 c l ? feedback bias resistor r b ?10 m ? ? series resistor (2), (3) r s ?? ? rc oscillator external r r ext see figure 18-1 rc oscillator external c c ext ?10 ? pf notes: 1. no more than 10% du ty cycle deviation from 50% 2. consult crystal vendor data sheet 3. not required for high frequency crystals 0 0 1020304050 14 12 10 8 6 4 2 resistor, r ext (k ? ) rc frequency, f rcclk (mhz) c ext = 10 pf 5v @ 25 c r ext c ext osc1 v dd mcu electrical specifications mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor electrical specifications 197 18.9 3v dc electrical characteristics table 18-7. dc electrica l characteristics (3v) characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?1.0ma) pta0?pta6, ptb0?ptb7, ptd0?ptd7 v oh v dd ?0.4 ??v output low voltage (i load = 0.8ma) pta6, ptb0?ptb7, ptd0, ptd1, ptd4, ptd5 v ol ??0.4v output low voltage (i load = 20ma) ptd6, ptd7 v ol ??0.5v led drives (v ol = 1.8v) pta0?pta5, ptd2, ptd3, ptd6, ptd7 i ol 4912ma input high voltage pta0?pta6, ptb0?ptb7, ptd0?ptd7, rst , irq 1 , osc1 v ih 0.7 v dd ? v dd v input low voltage pta0?pta6, ptb0?ptb7, ptd0?ptd7, rst , irq 1 , osc1 v il v ss ? 0.3 v dd v v dd supply current run, f op = 2mhz (3) wait (mc68hrc908xxx) (4) wait (mc68hc908xxx) (4) stop (5) ?40 c to 85 c i dd ? ? ? ? 5 1 4 1 8 1.3 4.5 5 ma ma ma a digital i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (6) v por 0?100mv por rise time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v dd +v hi 1.5 v dd ? 8.5 v pullup resistors (8) ptd6, ptd7 rst , irq1 , pta0?pta6 r pu1 r pu2 1.8 16 3.3 26 4.8 36 k ? k ? lv i r e s e t vo l t a g e v lv r 3 2.0 2.4 2.69 v electrical specifications technical data mc68h(r)c908jl3 ? rev. 1.1 198 electrical specifications freescale semiconductor 18.10 3v control timing notes: 1. v dd = 2.7 to 3.3 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source . all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f op = 4mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; all ports configured as inputs; osc2 capacitance linearly af- fects wait i dd . 5. stop i dd measured with osc1 grounded, no port pins sourcing current. lvi is disabled. 6. maximum is highest voltage that por is guaranteed. 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 8. r pu1 and r pu2 are measured at v dd = 5.0v table 18-8. control timing (3v) characteristic (1) notes: 1. v dd = 2.7 to 3.3 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor- mation. f op ?4mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 1.5 ? s table 18-7. dc electrica l characteristics (3v) characteristic (1) symbol min typ (2) max unit electrical specifications mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor electrical specifications 199 18.11 3v oscillator characteristics figure 18-2. rc vs . frequency (3v @25 c) table 18-9. oscillator component specifications (3v) characteristic symbol min typ max unit crystal frequency, xtalclk f oscxclk ?8 16mhz rc oscillator frequency, rcclk f rcclk 28 12mhz external clock reference frequency (1) f oscxclk dc ? 16 mhz crystal load capacitance (2) c l ?? ? crystal fixed capacitance (2) c 1 ? 2 c l ? crystal tuning capacitance (2) c 2 ? 2 c l ? feedback bias resistor r b ?10 m ? ? series resistor (2), (3) r s ?? ? rc oscillator external r r ext see figure 18-2 rc oscillator external c c ext ?10 ? pf notes: 1. no more than 10% du ty cycle deviation from 50% 2. consult crystal vendor data sheet 3. not required for high frequency crystals 0 0 1020304050 14 12 10 8 6 4 2 resistor, r ext (k ? ) rc frequency , f rcclk (mhz) c ext = 10 pf 3v @ 25 c r ext c ext osc1 v dd mcu electrical specifications technical data mc68h(r)c908jl3 ? rev. 1.1 200 electrical specifications freescale semiconductor 18.12 typical supply currents figure 18-3. typical operating i dd , with all modules turned on (25 c) figure 18-4. typi cal wait mode i dd , with adc turned on (25 c) figure 18-5. ty pical stop mode i dd , with all modul es disabled (25 c) 0 2 4 6 8 10 12 0123456789 5.5 v 3.3 v f op or f bus (mhz) i dd (ma) 14 mc68hrc908xxx 0 0.25 0.5 0.75 1 1.25 1.50 1.75 2 01 23 456 78 5.5 v 3.3 v i dd (ma) f op or f bus (mhz) mc68hrc908xxx 0 0.1 0.2 0.3 0.4 0.5 01 234 567 89 5.5 v 3.3 v f op or f bus (mhz) i dd ( a) mc68hrc908xxx electrical specifications mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor electrical specifications 201 18.13 adc characteristics table 18-10. adc characteristics characteristic symbol min max unit comments supply voltage v ddad 2.7 (v dd min) 5.5 (v dd max) v input voltages v adin v ss v dd v resolution b ad 88bits absolute accuracy a ad 0.5 1.5 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t aic = 1/f adic , tested only at 1 mhz conversion range r ad v ss v dd v power-up time t adpu 16 t aic cycles conversion time t adc 16 17 t aic cycles sample time (1) notes: 1. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. t ads 5? t aic cycles zero input reading (2) 2. zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. z adi 00 01 hex v in = v ss full-scale reading (3) f adi fe ff hex v in = v dd input capacitance c adi ? (20) 8 pf not tested input leakage (3) port b/port d 3. the external system error caused by input leakage current is approximately eq ual to the product of r source and input current. ?? 1 a electrical specifications technical data mc68h(r)c908jl3 ? rev. 1.1 202 electrical specifications freescale semiconductor 18.14 memory characteristics table 18-11. memory characteristics characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v flash program bus clock frequency ? 1 ? mhz flash read bus clock frequency f read (1) notes: 1. f read is defined as the frequency range for which the flash memory can be read. 32k 8m hz flash page erase time t erase (2) 2. if the page erase time is longer than t erase (min), there is no erase- disturb, but it reduces the endurance of the flash memory. 1?ms flash mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 4?ms flash pgm/erase to hven set up time t nvs 10 ? s flash high-voltage hold time t nvh 5? s flash high-voltage hold time (mass erase) t nvhl 100 ? s flash program hold time t pgs 5? s flash program time t prog 30 40 s flash return to read time t rcv (4) 4. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 1? s flash cumulative program hv period t hv (5) 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog 32) t hv max. ?4 ms flash row erase endurance (6) 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 10k ? cycles flash row program endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 10k ? cycles flash data retention time (8) 8. the flash is guaranteed to retain data over the entire operating temper ature range for at least the minimum time specified. ?10?years mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor mechanical specifications 203 technical data ? mc68h(r)c908jl3 section 19. mechanical specifications 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.3 20-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.4 20-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.5 28-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19.6 28-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19.2 introduction this section gives t he dimensions for: 20-pin plastic dual in -line package (case #738) 20-pin small outli ne integrated circuit package (case #751d) 28-pin plastic dual in -line package (case #710) 28-pin small outli ne integrated circuit package (case #751f) the following figures show the latest packa ge drawings at the time of this publication. to make sure that you have the latest package specifications, please visi t the freescale website at http://freescale.com. follow or worldwide web on-line instruct ions to retrieve the current mechanical specifications. mechanical specifications technical data mc68h(r)c908jl3 ? rev. 1.1 204 mechanical specifications freescale semiconductor 19.3 20-pin pdip figure 19-1. 20-pin pdip (case #738) 19.4 20-pin soic figure 19-2. 20-pi n soic (case #751d) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 ?a? seating plane k n f g d 20 pl ?t? m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ?a? ?b? 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c ?t? seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 mechanical specifications mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor mechanical specifications 205 19.5 28-pin pdip figure 19-3. 28-pin pdip (case #710) 19.6 28-pin soic figure 19-4. 28-p in soic (case #751f) notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 1 seating plane 15 14 28 m a b k c n f g d h j l dim min max min max inches millimeters a 36.45 37.21 1.435 1.465 b 13.72 14.22 0.540 0.560 c 3.94 5.08 0.155 0.200 d 0.36 0.56 0.014 0.022 f 1.02 1.52 0.040 0.060 g 2.54 bsc 0.100 bsc h 1.65 2.16 0.065 0.085 j 0.20 0.38 0.008 0.015 k 2.92 3.43 0.115 0.135 l 15.24 bsc 0.600 bsc m 0 15 0 15 n 0.51 1.02 0.020 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. j k f 1 15 14 28 -a- -b- 28x 14x d p s a m 0.010 (0.25) b s t m 0.010 (0.25) b m 26x g -t- seating plane c x 45 r m dim min max min max inches millimeters a 17.80 18.05 0.701 0.711 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m p 10.01 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 0 0 8 8 mechanical specifications technical data mc68h(r)c908jl3 ? rev. 1.1 206 mechanical specifications freescale semiconductor mc68h(r)c908jl3 ? rev. 1.1 technical data freescale semiconductor ordering information 207 technical data ? mc68h(r)c908jl3 section 20. ordering information 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 20.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 20.2 introduction this section contains ordering num bers for the mc68h(r)c908jl3, mc68h(r)c908jk3, and mc68h(r)c908jk1. ordering information technical data mc68h(r)c908jl3 ? rev. 1.1 208 ordering information freescale semiconductor 20.3 mc order numbers table 20-1. mc order numbers mc order number oscillator type flash memory package mc68hc908jl3cp mc68hc908jl3cdw mc68hc908jl3mp mc68hc908jl3mdw crystal oscillator 4096 bytes 28-pin package mc68hrc908jl3cp mc68hrc908jl3cdw mc68hrc908jl3mp mc68hrc908jl3mdw rc oscillator mc68HC908JK3cp mc68HC908JK3cdw mc68HC908JK3mp mc68HC908JK3mdw crystal oscillator 4096 bytes 20-pin package mc68hrc908jk3cp mc68hrc908jk3cdw mc68hrc908jk3mp mc68hrc908jk3mdw rc oscillator mc68HC908JK1cp mc68HC908JK1cdw crystal oscillator 1536 bytes mc68hrc908jk1cp mc68hrc908jk1cdw rc oscillator notes: c = ?40 c to +85 c m = ?40 c to +125 c (available for v dd = 5v only) p = plastic dual in-line package (pdip) dw = small outline integrated circuit package (soic) how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2005. all rights reserved. rev. 1.1 mc68hc908jl3/h august 1, 2005 |
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